DE69025121D1 - Clock control for a memory - Google Patents

Clock control for a memory

Info

Publication number
DE69025121D1
DE69025121D1 DE69025121T DE69025121T DE69025121D1 DE 69025121 D1 DE69025121 D1 DE 69025121D1 DE 69025121 T DE69025121 T DE 69025121T DE 69025121 T DE69025121 T DE 69025121T DE 69025121 D1 DE69025121 D1 DE 69025121D1
Authority
DE
Germany
Prior art keywords
memory
clock control
clock
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69025121T
Other languages
German (de)
Other versions
DE69025121T2 (en
Inventor
Andrew Timothy Ferris
Gordon Stirling Work
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
SGS Thomson Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Ltd filed Critical SGS Thomson Microelectronics Ltd
Publication of DE69025121D1 publication Critical patent/DE69025121D1/en
Application granted granted Critical
Publication of DE69025121T2 publication Critical patent/DE69025121T2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/926—Dummy metallization
DE69025121T 1989-10-12 1990-10-11 Clock control for a memory Expired - Fee Related DE69025121T2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB898923037A GB8923037D0 (en) 1989-10-12 1989-10-12 Timing control for a memory

Publications (2)

Publication Number Publication Date
DE69025121D1 true DE69025121D1 (en) 1996-03-14
DE69025121T2 DE69025121T2 (en) 1996-08-29

Family

ID=10664486

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69025121T Expired - Fee Related DE69025121T2 (en) 1989-10-12 1990-10-11 Clock control for a memory

Country Status (5)

Country Link
US (1) US5268869A (en)
EP (1) EP0422939B1 (en)
JP (1) JP2851408B2 (en)
DE (1) DE69025121T2 (en)
GB (1) GB8923037D0 (en)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0600142B1 (en) * 1992-11-30 1999-05-06 STMicroelectronics S.r.l. High performance single port RAM generator architecture
FR2707790B1 (en) * 1993-07-12 1995-09-15 Sgs Thomson Microelectronics Dual access memory.
JPH0750094A (en) * 1993-08-05 1995-02-21 Nec Corp Semiconductor memory circuit
EP0698884A1 (en) * 1994-08-24 1996-02-28 Advanced Micro Devices, Inc. Memory array for microprocessor cache
JP3132637B2 (en) * 1995-06-29 2001-02-05 日本電気株式会社 Nonvolatile semiconductor memory device
US5596539A (en) * 1995-12-28 1997-01-21 Lsi Logic Corporation Method and apparatus for a low power self-timed memory control system
DE69632574D1 (en) * 1996-03-29 2004-07-01 St Microelectronics Srl Data read management architecture for a memory device, especially non-volatile memory
EP0801393B1 (en) * 1996-04-09 2004-03-10 STMicroelectronics S.r.l. Circuit for determining completion of pre-charge of a generic bit line, particularly for non-volatile memories
FR2755286B1 (en) * 1996-10-25 1999-01-22 Sgs Thomson Microelectronics IMPROVED READ TIME MEMORY
EP0869506B1 (en) * 1997-04-03 2003-07-02 STMicroelectronics S.r.l. Memory device with reduced power dissipation
KR100256902B1 (en) * 1997-06-24 2000-05-15 김영환 Control circuit for semiconductor memory device
US6044024A (en) * 1998-01-14 2000-03-28 International Business Machines Corporation Interactive method for self-adjusted access on embedded DRAM memory macros
US6304486B1 (en) * 1999-12-20 2001-10-16 Fujitsu Limited Sensing time control device and method
KR100401509B1 (en) * 2001-05-31 2003-10-17 주식회사 하이닉스반도체 Sense amp circuit of semiconductor memory device
JP4837841B2 (en) * 2001-06-12 2011-12-14 富士通セミコンダクター株式会社 Static RAM
JP4339532B2 (en) 2001-07-25 2009-10-07 富士通マイクロエレクトロニクス株式会社 Static memory with self-timing circuit
JP4639030B2 (en) * 2002-11-18 2011-02-23 パナソニック株式会社 Semiconductor memory device
US6831853B2 (en) * 2002-11-19 2004-12-14 Taiwan Semiconductor Manufacturing Company Apparatus for cleaning a substrate
JP2004199759A (en) * 2002-12-17 2004-07-15 Fujitsu Ltd Semiconductor storage device
JP2004220721A (en) * 2003-01-16 2004-08-05 Matsushita Electric Ind Co Ltd Semiconductor memory device
JP4314056B2 (en) * 2003-04-17 2009-08-12 パナソニック株式会社 Semiconductor memory device
JP4514028B2 (en) * 2004-05-20 2010-07-28 ルネサスエレクトロニクス株式会社 Fault diagnosis circuit and fault diagnosis method
JP2007018584A (en) * 2005-07-06 2007-01-25 Matsushita Electric Ind Co Ltd Semiconductor storage device
FR2903524B1 (en) * 2006-07-05 2008-10-17 St Microelectronics Sa MEMORY DEVICE WITH PROGRAMMABLE CONTROL OF ACTIVATION OF READING AMPLIFIERS.
US7746717B1 (en) * 2007-09-07 2010-06-29 Xilinx, Inc. Desensitizing static random access memory (SRAM) to process variation
KR100866145B1 (en) * 2007-10-05 2008-10-31 주식회사 하이닉스반도체 Semiconductor device and biasing method thereof
JP2008052906A (en) * 2007-11-09 2008-03-06 Matsushita Electric Ind Co Ltd Semiconductor memory device
US9613714B1 (en) * 2016-01-19 2017-04-04 Ememory Technology Inc. One time programming memory cell and memory array for physically unclonable function technology and associated random code generating method
US10497414B1 (en) * 2018-06-08 2019-12-03 Arm Limited Circuitry for tracking bias voltage behavior

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4255679A (en) * 1978-10-30 1981-03-10 Texas Instruments Incorporated Depletion load dynamic sense amplifier for MOS random access memory
US4363111A (en) * 1980-10-06 1982-12-07 Heightley John D Dummy cell arrangement for an MOS memory
US4425633A (en) * 1980-10-06 1984-01-10 Mostek Corporation Variable delay circuit for emulating word line delay
JPS59203298A (en) * 1983-05-04 1984-11-17 Nec Corp Semiconductor memory
US4627032A (en) * 1983-11-25 1986-12-02 At&T Bell Laboratories Glitch lockout circuit for memory array

Also Published As

Publication number Publication date
EP0422939B1 (en) 1996-01-31
JPH03207086A (en) 1991-09-10
EP0422939A3 (en) 1991-09-04
US5268869A (en) 1993-12-07
JP2851408B2 (en) 1999-01-27
DE69025121T2 (en) 1996-08-29
EP0422939A2 (en) 1991-04-17
GB8923037D0 (en) 1989-11-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee