DE69015145D1 - Rechner mit cache-speicher. - Google Patents

Rechner mit cache-speicher.

Info

Publication number
DE69015145D1
DE69015145D1 DE69015145T DE69015145T DE69015145D1 DE 69015145 D1 DE69015145 D1 DE 69015145D1 DE 69015145 T DE69015145 T DE 69015145T DE 69015145 T DE69015145 T DE 69015145T DE 69015145 D1 DE69015145 D1 DE 69015145D1
Authority
DE
Germany
Prior art keywords
calculator
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69015145T
Other languages
English (en)
Other versions
DE69015145T2 (de
Inventor
David Wright
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE69015145D1 publication Critical patent/DE69015145D1/de
Application granted granted Critical
Publication of DE69015145T2 publication Critical patent/DE69015145T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69015145T 1989-07-05 1990-07-05 Rechner mit cache-speicher. Expired - Fee Related DE69015145T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB898915422A GB8915422D0 (en) 1989-07-05 1989-07-05 Computer with cache
PCT/GB1990/001037 WO1991000571A1 (en) 1989-07-05 1990-07-05 Computer with cache

Publications (2)

Publication Number Publication Date
DE69015145D1 true DE69015145D1 (de) 1995-01-26
DE69015145T2 DE69015145T2 (de) 1995-06-01

Family

ID=10659590

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69015145T Expired - Fee Related DE69015145T2 (de) 1989-07-05 1990-07-05 Rechner mit cache-speicher.

Country Status (8)

Country Link
US (1) US5293605A (de)
EP (1) EP0437558B1 (de)
JP (1) JPH04506125A (de)
AU (1) AU630533B2 (de)
CA (1) CA2035876C (de)
DE (1) DE69015145T2 (de)
GB (2) GB8915422D0 (de)
WO (1) WO1991000571A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5325503A (en) * 1992-02-21 1994-06-28 Compaq Computer Corporation Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3938097A (en) * 1974-04-01 1976-02-10 Xerox Corporation Memory and buffer arrangement for digital computers
US4816997A (en) * 1987-09-21 1989-03-28 Motorola, Inc. Bus master having selective burst deferral
JPH01112348A (ja) * 1987-10-26 1989-05-01 Oki Electric Ind Co Ltd データ転送方式
DE68923112T2 (de) * 1988-04-12 1995-11-30 Nippon Electric Co Mit einem Mikroprozessor verbundene Cachespeichersteuervorrichtung.
US5131083A (en) * 1989-04-05 1992-07-14 Intel Corporation Method of transferring burst data in a microprocessor
US5146582A (en) * 1989-06-19 1992-09-08 International Business Machines Corp. Data processing system with means to convert burst operations into memory pipelined operations
WO1991004536A1 (en) * 1989-09-20 1991-04-04 Dolphin Server Technology A/S Instruction cache architecture for parallel issuing of multiple instructions

Also Published As

Publication number Publication date
GB9103509D0 (en) 1991-04-17
AU6865091A (en) 1992-07-16
WO1991000571A1 (en) 1991-01-10
GB2240862A (en) 1991-08-14
GB2240862B (en) 1993-08-25
DE69015145T2 (de) 1995-06-01
CA2035876C (en) 1996-07-09
EP0437558A1 (de) 1991-07-24
EP0437558B1 (de) 1994-12-14
AU630533B2 (en) 1992-10-29
JPH04506125A (ja) 1992-10-22
US5293605A (en) 1994-03-08
CA2035876A1 (en) 1991-01-06
GB8915422D0 (en) 1989-08-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee