DE68928677D1 - Verfahren und digitaler Computer zur Vorverarbeitung mehrerer Befehle - Google Patents

Verfahren und digitaler Computer zur Vorverarbeitung mehrerer Befehle

Info

Publication number
DE68928677D1
DE68928677D1 DE68928677T DE68928677T DE68928677D1 DE 68928677 D1 DE68928677 D1 DE 68928677D1 DE 68928677 T DE68928677 T DE 68928677T DE 68928677 T DE68928677 T DE 68928677T DE 68928677 D1 DE68928677 D1 DE 68928677D1
Authority
DE
Germany
Prior art keywords
instruction
register
preprocessing
digital computer
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68928677T
Other languages
English (en)
Other versions
DE68928677T2 (de
Inventor
David B Fite
John E Murray
Michael M Mckeon
Mark A Firstenberg
William R Grundman
David A Webb
Ronald M Salett
Tryggve Fossum
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of DE68928677D1 publication Critical patent/DE68928677D1/de
Application granted granted Critical
Publication of DE68928677T2 publication Critical patent/DE68928677T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
  • Image Processing (AREA)
  • Executing Machine-Instructions (AREA)
DE68928677T 1989-02-03 1989-09-07 Verfahren und digitaler Computer zur Vorverarbeitung mehrerer Befehle Expired - Fee Related DE68928677T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/306,773 US5142631A (en) 1989-02-03 1989-02-03 System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register

Publications (2)

Publication Number Publication Date
DE68928677D1 true DE68928677D1 (de) 1998-06-25
DE68928677T2 DE68928677T2 (de) 1999-01-07

Family

ID=23186771

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68928677T Expired - Fee Related DE68928677T2 (de) 1989-02-03 1989-09-07 Verfahren und digitaler Computer zur Vorverarbeitung mehrerer Befehle

Country Status (7)

Country Link
US (1) US5142631A (de)
EP (1) EP0380850B1 (de)
JP (1) JPH02240735A (de)
AT (1) ATE166471T1 (de)
AU (1) AU632324B2 (de)
CA (1) CA2008238A1 (de)
DE (1) DE68928677T2 (de)

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US5450555A (en) * 1990-06-29 1995-09-12 Digital Equipment Corporation Register logging in pipelined computer using register log queue of register content changes and base queue of register log queue pointers for respective instructions
US5428811A (en) * 1990-12-20 1995-06-27 Intel Corporation Interface between a register file which arbitrates between a number of single cycle and multiple cycle functional units
US5341500A (en) * 1991-04-02 1994-08-23 Motorola, Inc. Data processor with combined static and dynamic masking of operand for breakpoint operation
US5615402A (en) * 1993-10-18 1997-03-25 Cyrix Corporation Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch
US6219773B1 (en) 1993-10-18 2001-04-17 Via-Cyrix, Inc. System and method of retiring misaligned write operands from a write buffer
US5740398A (en) * 1993-10-18 1998-04-14 Cyrix Corporation Program order sequencing of data in a microprocessor with write buffer
US5471598A (en) * 1993-10-18 1995-11-28 Cyrix Corporation Data dependency detection and handling in a microprocessor with write buffer
JP2750813B2 (ja) * 1994-03-23 1998-05-13 レオン自動機株式会社 クロワッサン生地の巻き上げ装置
US6128720A (en) * 1994-12-29 2000-10-03 International Business Machines Corporation Distributed processing array with component processors performing customized interpretation of instructions
US6101596A (en) * 1995-03-06 2000-08-08 Hitachi, Ltd. Information processor for performing processing without register conflicts
US6308261B1 (en) * 1998-01-30 2001-10-23 Hewlett-Packard Company Computer system having an instruction for probing memory latency
JP3710325B2 (ja) * 1999-06-07 2005-10-26 レオン自動機株式会社 食品生地の搬送装置
JP3766241B2 (ja) * 1999-09-08 2006-04-12 レオン自動機株式会社 食品生地供給装置
US6553483B1 (en) * 1999-11-29 2003-04-22 Intel Corporation Enhanced virtual renaming scheme and deadlock prevention therefor
US20030172253A1 (en) * 2002-03-06 2003-09-11 Sun Microsystems, Inc. Fast instruction dependency multiplexer
US20060095732A1 (en) * 2004-08-30 2006-05-04 Tran Thang M Processes, circuits, devices, and systems for scoreboard and other processor improvements
US8078845B2 (en) * 2005-12-16 2011-12-13 Freescale Semiconductor, Inc. Device and method for processing instructions based on masked register group size information
US7565511B2 (en) * 2006-03-13 2009-07-21 Sun Microsystems, Inc. Working register file entries with instruction based lifetime
US8667597B2 (en) * 2008-06-25 2014-03-04 Lockheed Martin Corporation Systems, methods, and products for secure code execution
JP6024281B2 (ja) * 2012-08-21 2016-11-16 富士通株式会社 プロセッサ
US9400650B2 (en) 2012-09-28 2016-07-26 Intel Corporation Read and write masks update instruction for vectorization of recursive computations over interdependent data
US10169039B2 (en) * 2015-04-24 2019-01-01 Optimum Semiconductor Technologies, Inc. Computer processor that implements pre-translation of virtual addresses
US10409606B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Verifying branch targets
US10175988B2 (en) 2015-06-26 2019-01-08 Microsoft Technology Licensing, Llc Explicit instruction scheduler state information for a processor
US10409599B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Decoding information about a group of instructions including a size of the group of instructions
US10169044B2 (en) 2015-06-26 2019-01-01 Microsoft Technology Licensing, Llc Processing an encoding format field to interpret header information regarding a group of instructions
US10191747B2 (en) 2015-06-26 2019-01-29 Microsoft Technology Licensing, Llc Locking operand values for groups of instructions executed atomically
US10346168B2 (en) 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
US9946548B2 (en) 2015-06-26 2018-04-17 Microsoft Technology Licensing, Llc Age-based management of instruction blocks in a processor instruction window
US9952867B2 (en) 2015-06-26 2018-04-24 Microsoft Technology Licensing, Llc Mapping instruction blocks based on block size
US10564929B2 (en) 2016-09-01 2020-02-18 Wave Computing, Inc. Communication between dataflow processing units and memories
US10505704B1 (en) * 2015-08-02 2019-12-10 Wave Computing, Inc. Data uploading to asynchronous circuitry using circular buffer control
US10659396B2 (en) 2015-08-02 2020-05-19 Wave Computing, Inc. Joining data within a reconfigurable fabric
US11977891B2 (en) 2015-09-19 2024-05-07 Microsoft Technology Licensing, Llc Implicit program order
US11681531B2 (en) 2015-09-19 2023-06-20 Microsoft Technology Licensing, Llc Generation and use of memory access instruction order encodings
US10871967B2 (en) 2015-09-19 2020-12-22 Microsoft Technology Licensing, Llc Register read/write ordering
US10678544B2 (en) 2015-09-19 2020-06-09 Microsoft Technology Licensing, Llc Initiating instruction block execution using a register access instruction
US11106976B2 (en) 2017-08-19 2021-08-31 Wave Computing, Inc. Neural network output layer for machine learning
US10949328B2 (en) 2017-08-19 2021-03-16 Wave Computing, Inc. Data flow graph computation using exceptions
US11645178B2 (en) 2018-07-27 2023-05-09 MIPS Tech, LLC Fail-safe semi-autonomous or autonomous vehicle processor array redundancy which permits an agent to perform a function based on comparing valid output from sets of redundant processors
US11227030B2 (en) 2019-04-01 2022-01-18 Wave Computing, Inc. Matrix multiplication engine using pipelining
US10997102B2 (en) 2019-04-01 2021-05-04 Wave Computing, Inc. Multidimensional address generation for direct memory access
US11481472B2 (en) 2019-04-01 2022-10-25 Wave Computing, Inc. Integer matrix multiplication engine using pipelining
US11934308B2 (en) 2019-04-01 2024-03-19 Wave Computing, Inc. Processor cluster address generation

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US4179737A (en) * 1977-12-23 1979-12-18 Burroughs Corporation Means and methods for providing greater speed and flexibility of microinstruction sequencing
FR2420168B1 (fr) * 1978-03-16 1986-09-26 Ibm Dispositif de pre-traitement d'instructions dans un systeme de traitement de donnees
US4367524A (en) * 1980-02-07 1983-01-04 Intel Corporation Microinstruction execution unit for use in a microprocessor
US4493019A (en) * 1980-05-06 1985-01-08 Burroughs Corporation Pipelined microprogrammed digital data processor employing microinstruction tasking
US4503535A (en) * 1982-06-30 1985-03-05 Intel Corporation Apparatus for recovery from failures in a multiprocessing system
US4667287A (en) * 1982-10-28 1987-05-19 Tandem Computers Incorporated Multiprocessor multisystem communications network
US4682284A (en) * 1984-12-06 1987-07-21 American Telephone & Telegraph Co., At&T Bell Lab. Queue administration method and apparatus
US4789925A (en) * 1985-07-31 1988-12-06 Unisys Corporation Vector data logical usage conflict detection
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US4903196A (en) * 1986-05-02 1990-02-20 International Business Machines Corporation Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor
US4891753A (en) * 1986-11-26 1990-01-02 Intel Corporation Register scorboarding on a microprocessor chip
JPH0760388B2 (ja) * 1987-06-09 1995-06-28 三菱電機株式会社 パイプライン制御回路
JPH07120278B2 (ja) * 1988-07-04 1995-12-20 三菱電機株式会社 データ処理装置

Also Published As

Publication number Publication date
AU5393690A (en) 1991-12-19
EP0380850A3 (de) 1991-10-23
CA2008238A1 (en) 1990-08-03
ATE166471T1 (de) 1998-06-15
JPH02240735A (ja) 1990-09-25
US5142631A (en) 1992-08-25
EP0380850A2 (de) 1990-08-08
EP0380850B1 (de) 1998-05-20
AU632324B2 (en) 1992-12-24
DE68928677T2 (de) 1999-01-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee