DE68927794T2 - Optimierung der Organisation mehrerer diskreter Elemente - Google Patents

Optimierung der Organisation mehrerer diskreter Elemente

Info

Publication number
DE68927794T2
DE68927794T2 DE68927794T DE68927794T DE68927794T2 DE 68927794 T2 DE68927794 T2 DE 68927794T2 DE 68927794 T DE68927794 T DE 68927794T DE 68927794 T DE68927794 T DE 68927794T DE 68927794 T2 DE68927794 T2 DE 68927794T2
Authority
DE
Germany
Prior art keywords
optimizing
organization
multiple discrete
discrete elements
elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68927794T
Other languages
English (en)
Other versions
DE68927794D1 (de
Inventor
Masahiko Toyonaga
Toshiro Akino
Hiroaki Okude
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE68927794D1 publication Critical patent/DE68927794D1/de
Publication of DE68927794T2 publication Critical patent/DE68927794T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q10/00—Administration; Management
    • G06Q10/04—Forecasting or optimisation specially adapted for administrative or management purposes, e.g. linear programming or "cutting stock problem"
    • G06Q10/047—Optimisation of routes or paths, e.g. travelling salesman problem
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Business, Economics & Management (AREA)
  • Theoretical Computer Science (AREA)
  • Human Resources & Organizations (AREA)
  • General Physics & Mathematics (AREA)
  • Economics (AREA)
  • Computer Hardware Design (AREA)
  • Strategic Management (AREA)
  • General Engineering & Computer Science (AREA)
  • Entrepreneurship & Innovation (AREA)
  • Geometry (AREA)
  • Quality & Reliability (AREA)
  • General Business, Economics & Management (AREA)
  • Operations Research (AREA)
  • Marketing (AREA)
  • Architecture (AREA)
  • Game Theory and Decision Science (AREA)
  • Evolutionary Computation (AREA)
  • Tourism & Hospitality (AREA)
  • Development Economics (AREA)
  • Data Mining & Analysis (AREA)
  • Databases & Information Systems (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
DE68927794T 1988-10-28 1989-10-27 Optimierung der Organisation mehrerer diskreter Elemente Expired - Fee Related DE68927794T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27343388 1988-10-28

Publications (2)

Publication Number Publication Date
DE68927794D1 DE68927794D1 (de) 1997-04-03
DE68927794T2 true DE68927794T2 (de) 1997-09-18

Family

ID=17527839

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68927794T Expired - Fee Related DE68927794T2 (de) 1988-10-28 1989-10-27 Optimierung der Organisation mehrerer diskreter Elemente

Country Status (4)

Country Link
US (1) US5159682A (de)
EP (1) EP0367154B1 (de)
KR (1) KR920005241B1 (de)
DE (1) DE68927794T2 (de)

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US5430831A (en) * 1991-03-19 1995-07-04 Koninklijke Ptt Nederland N.V. Method of packing rectangular objects in a rectangular area or space by determination of free subareas or subspaces
JP3220250B2 (ja) * 1992-01-09 2001-10-22 株式会社東芝 セル自動配置方法
JPH0773158A (ja) * 1993-07-12 1995-03-17 Hitachi Ltd 計画立案方法および装置
JP2922404B2 (ja) * 1993-11-15 1999-07-26 富士通株式会社 集積回路の配置決定方法
US5495419A (en) * 1994-04-19 1996-02-27 Lsi Logic Corporation Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing
US5815403A (en) * 1994-04-19 1998-09-29 Lsi Logic Corporation Fail-safe distributive processing method for producing a highest fitness cell placement for an integrated circuit chip
US5963975A (en) * 1994-04-19 1999-10-05 Lsi Logic Corporation Single chip integrated circuit distributed shared memory (DSM) and communications nodes
US5875117A (en) * 1994-04-19 1999-02-23 Lsi Logic Corporation Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system
US5914887A (en) * 1994-04-19 1999-06-22 Lsi Logic Corporation Congestion based cost factor computing apparatus for integrated circuit physical design automation system
US6155725A (en) * 1994-04-19 2000-12-05 Lsi Logic Corporation Cell placement representation and transposition for integrated circuit physical design automation system
US6493658B1 (en) 1994-04-19 2002-12-10 Lsi Logic Corporation Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithms
US5557533A (en) * 1994-04-19 1996-09-17 Lsi Logic Corporation Cell placement alteration apparatus for integrated circuit chip physical design automation system
US5587919A (en) * 1994-04-22 1996-12-24 Lucent Technologies, Inc. Apparatus and method for logic optimization by redundancy addition and removal
US5526514A (en) * 1994-06-21 1996-06-11 Pradhan; Dhiraj Method for circuit verification and multi-level circuit optimization based on structural implications
US5675500A (en) * 1994-10-18 1997-10-07 International Business Machines Corporation Multi-chip device partitioning process
US5852562A (en) * 1994-12-13 1998-12-22 Matsushita Electric Industrial Co., Ltd. Method and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce wiring zones
US5612894A (en) * 1995-02-08 1997-03-18 Wertz; David H. System and method for molecular modeling utilizing a sensitivity factor
US5740067A (en) * 1995-10-19 1998-04-14 International Business Machines Corporation Method for clock skew cost calculation
US5745735A (en) * 1995-10-26 1998-04-28 International Business Machines Corporation Localized simulated annealing
US5808899A (en) * 1996-06-28 1998-09-15 Lsi Logic Corporation Advanced modular cell placement system with cell placement crystallization
US5872718A (en) * 1996-06-28 1999-02-16 Lsi Logic Corporation Advanced modular cell placement system
US5812740A (en) * 1996-06-28 1998-09-22 Lsi Logic Corporation Advanced modular cell placement system with neighborhood system driven optimization
US5867398A (en) * 1996-06-28 1999-02-02 Lsi Logic Corporation Advanced modular cell placement system with density driven capacity penalty system
US5835381A (en) * 1996-06-28 1998-11-10 Lsi Logic Corporation Advanced modular cell placement system with minimizing maximal cut driven affinity system
US5870311A (en) * 1996-06-28 1999-02-09 Lsi Logic Corporation Advanced modular cell placement system with fast procedure for finding a levelizing cut point
US5963455A (en) * 1996-06-28 1999-10-05 Lsi Logic Corporation Advanced modular cell placement system with functional sieve optimization technique
US6030110A (en) * 1996-06-28 2000-02-29 Lsi Logic Corporation Advanced modular cell placement system with median control and increase in resolution
US5870312A (en) * 1996-06-28 1999-02-09 Lsi Logic Corporation Advanced modular cell placement system with dispersion-driven levelizing system
US5914888A (en) * 1996-06-28 1999-06-22 Lsi Logic Corporation Advanced modular cell placement system with coarse overflow remover
US5844811A (en) * 1996-06-28 1998-12-01 Lsi Logic Corporation Advanced modular cell placement system with universal affinity driven discrete placement optimization
US5892688A (en) * 1996-06-28 1999-04-06 Lsi Logic Corporation Advanced modular cell placement system with iterative one dimensional preplacement optimization
US6067409A (en) * 1996-06-28 2000-05-23 Lsi Logic Corporation Advanced modular cell placement system
US6026223A (en) * 1996-06-28 2000-02-15 Scepanovic; Ranko Advanced modular cell placement system with overlap remover with minimal noise
US6085032A (en) * 1996-06-28 2000-07-04 Lsi Logic Corporation Advanced modular cell placement system with sinusoidal optimization
US5831863A (en) * 1996-06-28 1998-11-03 Lsi Logic Corporation Advanced modular cell placement system with wire length driven affinity system
US5963728A (en) * 1996-08-14 1999-10-05 International Business Machines Corporation Method to partition clock sinks into nets
US5980093A (en) * 1996-12-04 1999-11-09 Lsi Logic Corporation Integrated circuit layout routing using multiprocessing
US6463347B1 (en) * 1997-09-15 2002-10-08 International Paper Company System for detecting occurrence of an event when the slope of change based upon difference of short and long term averages exceeds a predetermined limit
US6412096B1 (en) * 1999-04-30 2002-06-25 International Business Machines Corporation Method and apparatus for a hedge analysis technique for performance improvements of large scale integrated circuit logic design
US6769098B2 (en) * 2000-02-29 2004-07-27 Matsushita Electric Industrial Co., Ltd. Method of physical design for integrated circuit
US20030014225A1 (en) * 2001-07-13 2003-01-16 De Vicente Juan Francisco Thermodynamic simulated annealing schedule for combinatorial optimization problems
US6665851B1 (en) * 2001-12-04 2003-12-16 Synopsys, Inc. Quick placement of electronic circuits using orthogonal one dimensional placements
EP1320026A1 (de) * 2001-12-13 2003-06-18 STMicroelectronics S.r.l. Verfahren zum Generieren einer Zufallszahlensequenz und eines relativen Zufallbitgenerators
US7349121B2 (en) * 2002-08-02 2008-03-25 Agfa Graphics Nv Method for automatically determining an imposition plan
EP1387289A1 (de) * 2002-08-02 2004-02-04 Agfa-Gevaert Verfahren zur automatischen Erstellung eines Seitenumbruchplanes
TWI529551B (zh) * 2009-09-10 2016-04-11 卡登斯系統設計公司 用於實作圖形可編輯參數化單元之系統及方法
US11237527B2 (en) 2014-04-17 2022-02-01 Rovio Entertainment Ltd Parameter modification
EP2933693A1 (de) * 2014-04-17 2015-10-21 Rovio Entertainment Ltd Parameteränderung
DK3334282T3 (da) 2015-08-14 2023-03-27 Imertech Sas Uorganiske partikler indeholdende antimikrobielt metal

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1502554A (de) * 1965-12-01 1968-02-07
US3681782A (en) * 1970-12-02 1972-08-01 Honeywell Inf Systems Machine process for positioning interconnected components to minimize interconnecting line length
US4495559A (en) * 1981-11-02 1985-01-22 International Business Machines Corporation Optimization of an organization of many discrete elements
US4630219A (en) * 1983-11-23 1986-12-16 International Business Machines Corporation Element placement method
US4615011A (en) * 1983-12-19 1986-09-30 Ibm Iterative method for establishing connections and resulting product
US4754408A (en) * 1985-11-21 1988-06-28 International Business Machines Corporation Progressive insertion placement of elements on an integrated circuit
JPH0793358B2 (ja) * 1986-11-10 1995-10-09 日本電気株式会社 ブロック配置処理方式
US4931944A (en) * 1988-05-27 1990-06-05 General Motors Corporation Method of optimizing a vehicle assembly line build sequence

Also Published As

Publication number Publication date
KR920005241B1 (ko) 1992-06-29
EP0367154A2 (de) 1990-05-09
EP0367154A3 (de) 1991-10-16
EP0367154B1 (de) 1997-02-26
KR900006881A (ko) 1990-05-09
US5159682A (en) 1992-10-27
DE68927794D1 (de) 1997-04-03

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee