DE68927371D1 - Verfahren und Vorrichtung zur Verarbeitung von mehreren Zustandscodes wie für einen Parallel-Pipeline-Rechner - Google Patents

Verfahren und Vorrichtung zur Verarbeitung von mehreren Zustandscodes wie für einen Parallel-Pipeline-Rechner

Info

Publication number
DE68927371D1
DE68927371D1 DE68927371T DE68927371T DE68927371D1 DE 68927371 D1 DE68927371 D1 DE 68927371D1 DE 68927371 T DE68927371 T DE 68927371T DE 68927371 T DE68927371 T DE 68927371T DE 68927371 D1 DE68927371 D1 DE 68927371D1
Authority
DE
Germany
Prior art keywords
processing multiple
status codes
parallel pipeline
multiple status
pipeline computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68927371T
Other languages
English (en)
Other versions
DE68927371T2 (de
Inventor
Daniel Arthur Prener
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE68927371D1 publication Critical patent/DE68927371D1/de
Application granted granted Critical
Publication of DE68927371T2 publication Critical patent/DE68927371T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
DE68927371T 1989-01-09 1989-12-19 Verfahren und Vorrichtung zur Verarbeitung von mehreren Zustandscodes wie für einen Parallel-Pipeline-Rechner Expired - Fee Related DE68927371T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/294,850 US5125092A (en) 1989-01-09 1989-01-09 Method and apparatus for providing multiple condition code fields to to allow pipelined instructions contention free access to separate condition codes

Publications (2)

Publication Number Publication Date
DE68927371D1 true DE68927371D1 (de) 1996-11-28
DE68927371T2 DE68927371T2 (de) 1997-04-10

Family

ID=23135219

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68927371T Expired - Fee Related DE68927371T2 (de) 1989-01-09 1989-12-19 Verfahren und Vorrichtung zur Verarbeitung von mehreren Zustandscodes wie für einen Parallel-Pipeline-Rechner

Country Status (4)

Country Link
US (1) US5125092A (de)
EP (1) EP0378830B1 (de)
JP (1) JPH0776921B2 (de)
DE (1) DE68927371T2 (de)

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US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
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US5584009A (en) * 1993-10-18 1996-12-10 Cyrix Corporation System and method of retiring store data from a write buffer
US5471598A (en) * 1993-10-18 1995-11-28 Cyrix Corporation Data dependency detection and handling in a microprocessor with write buffer
US6219773B1 (en) 1993-10-18 2001-04-17 Via-Cyrix, Inc. System and method of retiring misaligned write operands from a write buffer
US5615402A (en) * 1993-10-18 1997-03-25 Cyrix Corporation Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch
US5740398A (en) * 1993-10-18 1998-04-14 Cyrix Corporation Program order sequencing of data in a microprocessor with write buffer
US5815695A (en) * 1993-10-28 1998-09-29 Apple Computer, Inc. Method and apparatus for using condition codes to nullify instructions based on results of previously-executed instructions on a computer processor
US5689695A (en) * 1993-11-30 1997-11-18 Texas Instruments Incorporated Conditional processor operation based upon result of two consecutive prior processor operations
US6058473A (en) * 1993-11-30 2000-05-02 Texas Instruments Incorporated Memory store from a register pair conditional upon a selected status bit
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US5539888A (en) * 1993-12-23 1996-07-23 Unisys Corporation System and method for processing external conditional branch instructions
US5748855A (en) * 1995-10-02 1998-05-05 Iinternational Business Machines Corporation Method and system for performance monitoring of misaligned memory accesses in a processing system
US5949971A (en) * 1995-10-02 1999-09-07 International Business Machines Corporation Method and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing system
US5751945A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing system
US5729726A (en) * 1995-10-02 1998-03-17 International Business Machines Corporation Method and system for performance monitoring efficiency of branch unit operation in a processing system
US5752062A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system
US5797019A (en) * 1995-10-02 1998-08-18 International Business Machines Corporation Method and system for performance monitoring time lengths of disabled interrupts in a processing system
US5691920A (en) * 1995-10-02 1997-11-25 International Business Machines Corporation Method and system for performance monitoring of dispatch unit efficiency in a processing system
US5845118A (en) * 1995-12-14 1998-12-01 International Business Machines Corporation Method for generating shared library executable code with lazy global offset table address calculation
US5991874A (en) * 1996-06-06 1999-11-23 Intel Corporation Conditional move using a compare instruction generating a condition field
US5859998A (en) * 1997-03-19 1999-01-12 Advanced Micro Devices, Inc. Hierarchical microcode implementation of floating point instructions for a microprocessor
US5828873A (en) * 1997-03-19 1998-10-27 Advanced Micro Devices, Inc. Assembly queue for a floating point unit
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US6370639B1 (en) * 1998-10-10 2002-04-09 Institute For The Development Of Emerging Architectures L.L.C. Processor architecture having two or more floating-point status fields
US6842853B1 (en) * 1999-01-13 2005-01-11 Sun Microsystems, Inc. Thread suspension system and method
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GB2352536A (en) * 1999-07-21 2001-01-31 Element 14 Ltd Conditional instruction execution
US6574728B1 (en) * 1999-08-10 2003-06-03 Cirrus Logic, Inc. Condition code stack architecture systems and methods
US6971000B1 (en) * 2000-04-13 2005-11-29 International Business Machines Corporation Use of software hint for branch prediction in the absence of hint bit in the branch instruction
US7043518B2 (en) * 2003-07-31 2006-05-09 Cradle Technologies, Inc. Method and system for performing parallel integer multiply accumulate operations on packed data
US9069547B2 (en) 2006-09-22 2015-06-30 Intel Corporation Instruction and logic for processing text strings
US20130275725A1 (en) * 2011-01-03 2013-10-17 Freescale Semiconductor, Inc. Integrated circuit device and method for performing conditional negation of data
US10067766B2 (en) * 2015-02-26 2018-09-04 International Business Machines Corporation History buffer with hybrid entry support for multiple-field registers
US9971604B2 (en) 2015-02-26 2018-05-15 International Business Machines Corporation History buffer for multiple-field registers
US9996353B2 (en) 2015-02-26 2018-06-12 International Business Machines Corporation Universal history buffer to support multiple register types
EP3462308B1 (de) * 2017-09-29 2022-03-02 ARM Limited Transaktionsverschachtelungstiefentestanweisung

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Also Published As

Publication number Publication date
EP0378830A2 (de) 1990-07-25
EP0378830A3 (de) 1992-09-02
JPH0776921B2 (ja) 1995-08-16
EP0378830B1 (de) 1996-10-23
US5125092A (en) 1992-06-23
DE68927371T2 (de) 1997-04-10
JPH02226342A (ja) 1990-09-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee