DE68927371D1 - Verfahren und Vorrichtung zur Verarbeitung von mehreren Zustandscodes wie für einen Parallel-Pipeline-Rechner - Google Patents
Verfahren und Vorrichtung zur Verarbeitung von mehreren Zustandscodes wie für einen Parallel-Pipeline-RechnerInfo
- Publication number
- DE68927371D1 DE68927371D1 DE68927371T DE68927371T DE68927371D1 DE 68927371 D1 DE68927371 D1 DE 68927371D1 DE 68927371 T DE68927371 T DE 68927371T DE 68927371 T DE68927371 T DE 68927371T DE 68927371 D1 DE68927371 D1 DE 68927371D1
- Authority
- DE
- Germany
- Prior art keywords
- processing multiple
- status codes
- parallel pipeline
- multiple status
- pipeline computer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30094—Condition code generation, e.g. Carry, Zero flag
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/294,850 US5125092A (en) | 1989-01-09 | 1989-01-09 | Method and apparatus for providing multiple condition code fields to to allow pipelined instructions contention free access to separate condition codes |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68927371D1 true DE68927371D1 (de) | 1996-11-28 |
DE68927371T2 DE68927371T2 (de) | 1997-04-10 |
Family
ID=23135219
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE68927371T Expired - Fee Related DE68927371T2 (de) | 1989-01-09 | 1989-12-19 | Verfahren und Vorrichtung zur Verarbeitung von mehreren Zustandscodes wie für einen Parallel-Pipeline-Rechner |
Country Status (4)
Country | Link |
---|---|
US (1) | US5125092A (de) |
EP (1) | EP0378830B1 (de) |
JP (1) | JPH0776921B2 (de) |
DE (1) | DE68927371T2 (de) |
Families Citing this family (48)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6253307B1 (en) * | 1989-05-04 | 2001-06-26 | Texas Instruments Incorporated | Data processing device with mask and status bits for selecting a set of status conditions |
FR2656442B1 (fr) * | 1989-12-21 | 1994-07-29 | Bull Sa | Processeur a plusieurs unites microprogrammees avec mecanisme d'execution anticipee des instructions. |
US5287522A (en) * | 1990-06-29 | 1994-02-15 | Bull Hn Information Systems, Inc. | External procedure invocation apparatus utilizing internal branch vector interrupts and vector address generation, in a RISC chip |
US5630157A (en) * | 1991-06-13 | 1997-05-13 | International Business Machines Corporation | Computer organization for multiple and out-of-order execution of condition code testing and setting instructions |
JPH06110688A (ja) * | 1991-06-13 | 1994-04-22 | Internatl Business Mach Corp <Ibm> | 複数の順序外れ命令を並行処理するためのコンピュータ・システム |
US5493687A (en) * | 1991-07-08 | 1996-02-20 | Seiko Epson Corporation | RISC microprocessor architecture implementing multiple typed register sets |
US5539911A (en) | 1991-07-08 | 1996-07-23 | Seiko Epson Corporation | High-performance, superscalar-based computer system with out-of-order instruction execution |
US5345568A (en) * | 1991-09-19 | 1994-09-06 | Chips And Technologies, Inc. | Instruction fetch circuit which allows for independent decoding and execution of instructions |
DE69311330T2 (de) | 1992-03-31 | 1997-09-25 | Seiko Epson Corp | Befehlsablauffolgeplanung von einem risc-superskalarprozessor |
DE69308548T2 (de) | 1992-05-01 | 1997-06-12 | Seiko Epson Corp | Vorrichtung und verfahren zum befehlsabschluss in einem superskalaren prozessor. |
FR2693573B1 (fr) * | 1992-07-13 | 1994-09-30 | Texas Instruments France | Système de traitement de données à registre d'état dont la mise à jour dépend du programme. |
US5628021A (en) | 1992-12-31 | 1997-05-06 | Seiko Epson Corporation | System and method for assigning tags to control instruction processing in a superscalar processor |
DE69330889T2 (de) | 1992-12-31 | 2002-03-28 | Seiko Epson Corp | System und Verfahren zur Änderung der Namen von Registern |
US5584009A (en) * | 1993-10-18 | 1996-12-10 | Cyrix Corporation | System and method of retiring store data from a write buffer |
US5471598A (en) * | 1993-10-18 | 1995-11-28 | Cyrix Corporation | Data dependency detection and handling in a microprocessor with write buffer |
US5740398A (en) * | 1993-10-18 | 1998-04-14 | Cyrix Corporation | Program order sequencing of data in a microprocessor with write buffer |
US6219773B1 (en) | 1993-10-18 | 2001-04-17 | Via-Cyrix, Inc. | System and method of retiring misaligned write operands from a write buffer |
US5615402A (en) * | 1993-10-18 | 1997-03-25 | Cyrix Corporation | Unified write buffer having information identifying whether the address belongs to a first write operand or a second write operand having an extra wide latch |
US5815695A (en) * | 1993-10-28 | 1998-09-29 | Apple Computer, Inc. | Method and apparatus for using condition codes to nullify instructions based on results of previously-executed instructions on a computer processor |
US5689695A (en) * | 1993-11-30 | 1997-11-18 | Texas Instruments Incorporated | Conditional processor operation based upon result of two consecutive prior processor operations |
US6058473A (en) * | 1993-11-30 | 2000-05-02 | Texas Instruments Incorporated | Memory store from a register pair conditional upon a selected status bit |
US6026484A (en) * | 1993-11-30 | 2000-02-15 | Texas Instruments Incorporated | Data processing apparatus, system and method for if, then, else operation using write priority |
US5539888A (en) * | 1993-12-23 | 1996-07-23 | Unisys Corporation | System and method for processing external conditional branch instructions |
US5691920A (en) * | 1995-10-02 | 1997-11-25 | International Business Machines Corporation | Method and system for performance monitoring of dispatch unit efficiency in a processing system |
US5729726A (en) * | 1995-10-02 | 1998-03-17 | International Business Machines Corporation | Method and system for performance monitoring efficiency of branch unit operation in a processing system |
US5797019A (en) * | 1995-10-02 | 1998-08-18 | International Business Machines Corporation | Method and system for performance monitoring time lengths of disabled interrupts in a processing system |
US5752062A (en) * | 1995-10-02 | 1998-05-12 | International Business Machines Corporation | Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system |
US5751945A (en) * | 1995-10-02 | 1998-05-12 | International Business Machines Corporation | Method and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing system |
US5748855A (en) * | 1995-10-02 | 1998-05-05 | Iinternational Business Machines Corporation | Method and system for performance monitoring of misaligned memory accesses in a processing system |
US5949971A (en) * | 1995-10-02 | 1999-09-07 | International Business Machines Corporation | Method and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing system |
US5845118A (en) * | 1995-12-14 | 1998-12-01 | International Business Machines Corporation | Method for generating shared library executable code with lazy global offset table address calculation |
US5991874A (en) * | 1996-06-06 | 1999-11-23 | Intel Corporation | Conditional move using a compare instruction generating a condition field |
US5859998A (en) * | 1997-03-19 | 1999-01-12 | Advanced Micro Devices, Inc. | Hierarchical microcode implementation of floating point instructions for a microprocessor |
US5828873A (en) * | 1997-03-19 | 1998-10-27 | Advanced Micro Devices, Inc. | Assembly queue for a floating point unit |
JPH1173301A (ja) * | 1997-08-29 | 1999-03-16 | Matsushita Electric Ind Co Ltd | 情報処理装置 |
US6370639B1 (en) * | 1998-10-10 | 2002-04-09 | Institute For The Development Of Emerging Architectures L.L.C. | Processor architecture having two or more floating-point status fields |
US6842853B1 (en) * | 1999-01-13 | 2005-01-11 | Sun Microsystems, Inc. | Thread suspension system and method |
GB2352308B (en) * | 1999-07-21 | 2004-06-30 | Element 14 Ltd | Accessing a test condition |
GB2352536A (en) * | 1999-07-21 | 2001-01-31 | Element 14 Ltd | Conditional instruction execution |
US6574728B1 (en) * | 1999-08-10 | 2003-06-03 | Cirrus Logic, Inc. | Condition code stack architecture systems and methods |
US6971000B1 (en) * | 2000-04-13 | 2005-11-29 | International Business Machines Corporation | Use of software hint for branch prediction in the absence of hint bit in the branch instruction |
US7043518B2 (en) * | 2003-07-31 | 2006-05-09 | Cradle Technologies, Inc. | Method and system for performing parallel integer multiply accumulate operations on packed data |
US9069547B2 (en) | 2006-09-22 | 2015-06-30 | Intel Corporation | Instruction and logic for processing text strings |
WO2012093288A1 (en) * | 2011-01-03 | 2012-07-12 | Freescale Semiconductor, Inc. | Integrated circuit device and method for performing conditional negation of data |
US10067766B2 (en) * | 2015-02-26 | 2018-09-04 | International Business Machines Corporation | History buffer with hybrid entry support for multiple-field registers |
US9971604B2 (en) | 2015-02-26 | 2018-05-15 | International Business Machines Corporation | History buffer for multiple-field registers |
US9996353B2 (en) | 2015-02-26 | 2018-06-12 | International Business Machines Corporation | Universal history buffer to support multiple register types |
EP3462308B1 (de) * | 2017-09-29 | 2022-03-02 | ARM Limited | Transaktionsverschachtelungstiefentestanweisung |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4136383A (en) * | 1974-10-01 | 1979-01-23 | Nippon Telegraph And Telephone Public Corporation | Microprogrammed, multipurpose processor having controllable execution speed |
US4348721A (en) * | 1978-06-30 | 1982-09-07 | International Business Machines Corporation | System for selectively addressing nested link return addresses in a microcontroller |
US4370710A (en) * | 1980-08-26 | 1983-01-25 | Control Data Corporation | Cache memory organization utilizing miss information holding registers to prevent lockup from cache misses |
US4532589A (en) * | 1981-12-02 | 1985-07-30 | Hitachi, Ltd. | Digital data processor with two operation units |
JPS60110043A (ja) * | 1983-11-18 | 1985-06-15 | Nec Corp | 情報処理装置 |
US4847755A (en) * | 1985-10-31 | 1989-07-11 | Mcc Development, Ltd. | Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies |
US4748585A (en) * | 1985-12-26 | 1988-05-31 | Chiarulli Donald M | Processor utilizing reconfigurable process segments to accomodate data word length |
US4809169A (en) * | 1986-04-23 | 1989-02-28 | Advanced Micro Devices, Inc. | Parallel, multiple coprocessor computer architecture having plural execution modes |
US4766566A (en) * | 1986-08-18 | 1988-08-23 | International Business Machines Corp. | Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing |
US4994964A (en) * | 1987-04-16 | 1991-02-19 | L & C Family Partnership | Transaction tracking data processing system |
US4980850A (en) * | 1987-05-14 | 1990-12-25 | Digital Equipment Corporation | Automatic sizing memory system with multiplexed configuration signals at memory modules |
JPH0616617B2 (ja) * | 1987-12-07 | 1994-03-02 | 富士通株式会社 | 初期条件設定方法 |
-
1989
- 1989-01-09 US US07/294,850 patent/US5125092A/en not_active Expired - Fee Related
- 1989-12-19 DE DE68927371T patent/DE68927371T2/de not_active Expired - Fee Related
- 1989-12-19 EP EP89123426A patent/EP0378830B1/de not_active Expired - Lifetime
-
1990
- 1990-01-09 JP JP2001127A patent/JPH0776921B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH02226342A (ja) | 1990-09-07 |
EP0378830B1 (de) | 1996-10-23 |
US5125092A (en) | 1992-06-23 |
EP0378830A2 (de) | 1990-07-25 |
DE68927371T2 (de) | 1997-04-10 |
JPH0776921B2 (ja) | 1995-08-16 |
EP0378830A3 (de) | 1992-09-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |