DE68922668T2 - Multiplexeinrichtung. - Google Patents

Multiplexeinrichtung.

Info

Publication number
DE68922668T2
DE68922668T2 DE68922668T DE68922668T DE68922668T2 DE 68922668 T2 DE68922668 T2 DE 68922668T2 DE 68922668 T DE68922668 T DE 68922668T DE 68922668 T DE68922668 T DE 68922668T DE 68922668 T2 DE68922668 T2 DE 68922668T2
Authority
DE
Germany
Prior art keywords
multiplexing device
multiplexing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68922668T
Other languages
English (en)
Other versions
DE68922668D1 (de
Inventor
Yoshiko Mitsubishi Denk Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE68922668D1 publication Critical patent/DE68922668D1/de
Application granted granted Critical
Publication of DE68922668T2 publication Critical patent/DE68922668T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/16Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605Fixed allocated frame structures
    • H04J3/1623Plesiochronous digital hierarchy [PDH]
    • H04J3/1641Hierarchical systems
DE68922668T 1988-08-05 1989-07-26 Multiplexeinrichtung. Expired - Fee Related DE68922668T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63195703A JPH0691507B2 (ja) 1988-08-05 1988-08-05 多重化装置

Publications (2)

Publication Number Publication Date
DE68922668D1 DE68922668D1 (de) 1995-06-22
DE68922668T2 true DE68922668T2 (de) 1996-02-15

Family

ID=16345575

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68922668T Expired - Fee Related DE68922668T2 (de) 1988-08-05 1989-07-26 Multiplexeinrichtung.

Country Status (4)

Country Link
US (1) US4979166A (de)
EP (1) EP0353610B1 (de)
JP (1) JPH0691507B2 (de)
DE (1) DE68922668T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2625054B1 (fr) * 1987-12-18 1990-05-04 Trt Telecom Radio Electr Dispositif de transformation de paquets de donnees en un multiplex regulier pour systeme de transmission utilisant le principe d'a.m.r.t.
JP2962787B2 (ja) * 1990-08-10 1999-10-12 富士通株式会社 通信制御方式
US5164940A (en) * 1991-05-31 1992-11-17 Mitel Corporation Modular communication system with allocatable bandwidth
JPH07123067A (ja) * 1993-10-20 1995-05-12 Hitachi Ltd 多重化装置
US6043684A (en) * 1995-12-20 2000-03-28 Cypress Semiconductor Corp. Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit
US5903174A (en) * 1995-12-20 1999-05-11 Cypress Semiconductor Corp. Method and apparatus for reducing skew among input signals within an integrated circuit
US5835970A (en) * 1995-12-21 1998-11-10 Cypress Semiconductor Corp. Burst address generator having two modes of operation employing a linear/nonlinear counter using decoded addresses
US6411140B1 (en) 1995-12-20 2002-06-25 Cypress Semiconductor Corporation Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit
JP3408720B2 (ja) * 1996-06-13 2003-05-19 富士通株式会社 高速同期多重化装置
US6901971B2 (en) 2001-01-10 2005-06-07 Entegris, Inc. Transportable container including an internal environment monitor
JP4738290B2 (ja) * 2006-09-08 2011-08-03 三菱農機株式会社 コンバイン
CN102302935B (zh) * 2011-05-31 2014-05-07 武汉科林精细化工有限公司 一种用于油品加氢脱芳烃的催化剂及其制备方法
JP7395937B2 (ja) 2019-10-08 2023-12-12 Toppanホールディングス株式会社 品物の箱詰めシステム

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH514268A (de) * 1970-09-30 1971-10-15 Ibm Verfahren zur Zeitmultiplex-Nachrichtenübertragung und Vermittlungseinrichtung zur Durchführung des Verfahrens
US4375681A (en) * 1980-06-03 1983-03-01 Rockwell International Corporation Protected muldem with interchangeable circuits of different data rates
US4685101A (en) * 1984-12-20 1987-08-04 Siemens Aktiengesellschaft Digital multiplexer for PCM voice channels having a cross-connect capability
US4697262A (en) * 1984-12-20 1987-09-29 Siemens Aktiengesellschaft Digital carrier channel bus interface module for a multiplexer having a cross-connect bus system
JPS61163742A (ja) * 1985-01-12 1986-07-24 Nec Corp 秘話装置
US4815074A (en) * 1986-08-01 1989-03-21 General Datacomm, Inc. High speed bit interleaved time division multiplexer for multinode communication systems
US4885741A (en) * 1988-08-03 1989-12-05 American Telephone And Telegraph Company Data communication arrangement with embedded matrix switch

Also Published As

Publication number Publication date
US4979166A (en) 1990-12-18
JPH0244934A (ja) 1990-02-14
JPH0691507B2 (ja) 1994-11-14
EP0353610A2 (de) 1990-02-07
EP0353610A3 (de) 1991-07-17
DE68922668D1 (de) 1995-06-22
EP0353610B1 (de) 1995-05-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee