DE68921091T2 - Multiplex circuit. - Google Patents

Abstract

A multiplexer circuit for effecting in successive phases of operation thereof actuation of selected devices of respective groups of devices of a series of capacitance actuated devices has a series of parallel electrical paths to which the respective devices are connected. A signal generator is connected across said paths and two capacitors of each device are connected between the path of the associated device and the respective paths on opposite sides of the path of the associated device. First and second switching means are disposed in each path and are closed by respective logic signals applied thereto so that when the first and second switching means of one path are respectively closed and open and the first and second switching means of each of the paths on respective opposite sides of that one path are respectively open and closed, charging of the capacitors connected to that one path takes place and when thereafter the first and second switching means of that one path are respectively open and closed discharge of the capacitors connected to that one path takes place.

Description

The invention relates to multiplexed circuits for effecting, in successive operating phases, actuation of selected devices of different groups of devices of a series of capacitively actuated devices.

One application of such a multiplex circuit is a pulsed droplet applying device, such as an on-demand inkjet printer with a multi-channel arrangement from whose channels the droplets are ejected and in which the channels are arranged in groups; here channels from the respective groups are selected for printing droplets in successive operating phases of the multiplex circuit. In known forms of pulsed droplet inkjet printers, so-called on-demand printers, circuits must be designed accordingly for considerable operating currents and with such currents there is a risk of a burn-through defect. One aim of the invention is to create a multiplex circuit for such an application which is designed or used only for a relatively low power. Furthermore, in known forms of pulsed droplet inkjet printers, the switching of the considerable operating currents leads to high frequency interference. Therefore, a further object of the invention is to minimize such interference.

GB-A-2 104 005 describes a circuit for operating a single capacitively operated device with two parallel electrical paths, each of which has a first and a second switching device.

The present invention relates to a multiplexed circuit for causing, in successive operating phases, actuation of selected devices of different groups of devices of a series of capacitively actuated devices, characterized in that the circuit comprises a series of parallel electrical paths by which the respective devices can be connected, the paths being used to connect in parallel to a signal generator two capacitors of each device connected between the path of the associated device and the respective paths on different sides of said path of the associated device, and first and second switching means arranged in each path and used to be closed by correspondingly applied logic signals, so that when the first and second switching means of one path are closed and open respectively and the first and second switching means of each of the paths on respective different sides of said one path are open and closed respectively, charging of the capacitors connected to said one path takes place, and when thereafter the first and second switching means of said one path are open and closed respectively, a discharge of the capacitors connected to said one path takes place.

Furthermore, a diode is connected in parallel with the second switching means of each path and provides a conductive path for discharging capacitors connected between the path in which the diode is connected and the paths on respective opposite sides.

Advantageously, the first and second switching means are an integrated silicon chip circuit, wherein the switching means comprise transistor switches. Accordingly, the transistors comprise field effect transistors.

In an embodiment of a multiplex circuit according to the invention, the second switching means of each path comprises first and second switching components, of which the first switching component provides a bypass path parallel to the second switching component during charging of the capacitors connected between the path containing the second switching means and the paths on the different sides thereof by means of the first switching means in the paths on the different sides of the path containing the second switching means, while the second switching component provides a conductive path for discharging the capacitors connected to the path containing the second switching component after charging them by means of the first switching means contained in the same path as the second switching component. Furthermore, the first and second switching means are provided on an integrated silicon chip circuit, the first switching means comprising a field effect transistor and the first and second switching components of the second switching means each comprising a field effect transistor which has the conductivity of a bipolar transistor.

Thus, in each phase of operation, the capacitors connected to devices selected for actuation are charged in an initial portion of a voltage waveform supplied by the signal generator after the signal generator is disconnected from the circuit for a further interval of the waveform prior to discharging the charged capacitors. Here, the signal generator and the parallel electrical paths and their first and second switching means are formed on a silicon chip integrated circuit.

According to an advantageous feature of the invention, in which actuation of each selected device is required to produce a substantially identical effect, and in which actuation with a device is influenced by the actuated or non-actuated state of devices on different sides of the actuated device, it is important to effect actuation of each selected device in accordance with the actuated or non-actuated state of devices adjacent to each selected device. To this end, the logic signal applying means is used to apply signals to the first and second switching means to enable charging of the capacitors of each of the devices selected for actuation over a corresponding period of time in dependence on the actuated or non-actuated state of devices adjacent to each of the selected devices.

The invention further relates to an electrically pulsed device having a multi-channel arrangement for applying liquid droplets to a surface, comprising a droplet application head formed of electrically active material, a plurality of channels for liquid formed in the head and arranged in a number of groups, nozzles communicating with the respective channels, longitudinal channel side walls each serving to separate one channel from the next, and electrically operable means for causing transverse displacement in opposite directions to the longitudinal side walls of each channel, the electrically operable means comprising electrodes in each channel on the respective opposite surfaces of the longitudinal channel side walls, conductive means connecting the electrodes in each channel, the electrodes and the longitudinal channel side walls forming a series of capacitors, each consisting of one of said longitudinal channel side walls and the electrodes on the opposite sides, and comprising a multiplexed circuit for causing actuation of the longitudinal channel walls of selected channels in the respective channel groups in successive phases of operation, the circuit comprising a series of parallel electrical paths, the capacitors each being connected between successive paths of said electrical paths, a signal generator connected in parallel with the parallel electrical paths, first and second switching means arranged in each of said paths, and logic signal applying means for causing conduction of the first and second switching means so that when the first and second switching means of one path are closed or open respectively, and the first and second switching means of each of the paths on different sides of said one path are open or closed respectively, charging of the capacitors connected to said one path takes place, and when thereafter the first and second switching means of said one path are open or closed respectively, discharging of the capacitors takes place.

In a pulsed droplet applicator according to the invention, crosstalk due to channel wall compliance, i.e. due to the effect of pressures in an actuated channel which are present in adjacent channels, can be electrically compensated for in accordance with an important feature of the invention. To achieve such compensation, the logic signal applying means are used to apply signals to the first and second switching means in each of the parallel paths to which the capacitors of selected channels are connected to enable the capacitors of each selected channel to be charged in a time interval to provide a voltage level in dependence on of the selected or non-selected state of adjacent channels of the group containing the selected channels.

Furthermore, the signal generator is used during charging of the capacitors to apply a signal to the capacitors of the selected channels having a relatively slowly rising voltage, and the logic signal applying means are used to cause the signal generator to be disconnected from the capacitors of the selected channels when a predetermined charging voltage is reached and, after an interval for operating the switching means, to cause a rapid discharging of the charged capacitors, whereby during charging of the capacitors of the selected channels the longitudinal side walls of said channels are displaced relatively slowly outwards and during discharging of the capacitors the channel walls are rapidly returned.

The invention will now be described by way of example with reference to the accompanying diagrammatic drawings, of which:

Fig.1 is a sectional view of an ink jet print head with thrust wall actuators as described in EP-A-0 278 590;

Fig.2 illustrates one form of multiplexed circuit connected to the push mode actuators of the print head shown in Fig.1;

Fig.3 illustrates another form of multiplexed circuit for use in conjunction with the push mode actuators of Fig.1, and

Fig.4 shows a corresponding waveform for actuating the inkjet print head of Fig.1 which uses the circuitry of either Fig.2 or Fig.3.

In the drawings, the same parts are provided with the same reference symbols.

Fig.1 shows a module part 10 of an ink jet print head 12 in which a plurality of closely spaced ink drop ejectors are arranged side by side in an array. The ejectors consist of elongated parallel channels 20 to 28 which are filled with ink and separated by piezoelectric thrust wall actuators 30 to 39 as described in EP-A-0 278 590.

The ink channels 20-28 have electrodes 40-48 covering the walls of each channel, which provide actuation electrodes for the wall actuators, and which together with the wall actuators effectively form capacitors 50-58. The electrodes are connected via traces/lines 70-78 to terminals 60-68 of a silicon chip integrated circuit, as will be described below.

As explained in the pending European patent application, the ink drop ejectors are divided separately into two groups of odd and even numbered channels and selected channels in the odd and even numbered groups are actuated in alternating cycles. In a typical cycle, an operation is performed by holding the electrodes of one group (e.g. the even numbered channels) at ground potential and applying a voltage waveform to those channels to print in the odd group of channels.

A typical multiplexer control circuit is shown in Fig.2, which shows a signal generator 100 provided in a silicon chip integrated circuit 101 and connected in parallel to internal buses 101 and 103, bus 102 being connected to the positive output terminal of the signal generator and bus 103 to its negative output terminal which is held at ground potential. Between buses 102 and 103 there are provided parallel electrical paths associated with the channels, of which only paths 113 to 117 are shown, and these include terminals 63 to 67.

Field effect transistors 123 to 127 are connected in paths 113 to 117 between bus 102 and terminals 63 to 67, to whose gate electrodes an internally generated logic signal can be applied, as will be described below, in order to make the device conductive.

Between terminals 63 to 67 and bus 103, paths 113 to 117 comprise the collector-emitter paths of bipolar n-p-n transistors 133 to 137. The base-emitter paths of these devices include field-effect transistors 143 to 147, to whose gate electrodes internally generated logic signals can be applied in order to render these devices conductive. The collector-emitter paths of devices 133-137 are shunted by respective field effect transistors 153-157 having their gates connected to the gates of devices 143-147 so that these devices are rendered conductive by the same logic signals to thereby activate devices 143-147. Devices 153-157 are themselves shunted by diodes 163-167 which provide capacitor discharge paths as will be described below.

The logic signals to cause and stop the conduction of transistors 123 to 127, 143 to 147 and 153 to 157, are supplied by registers 173 to 177 of a logic block 178 to which print pattern data are applied on a line 179 and relatively high frequency clock pulses on a line 189, which is also connected to the signal generator 100, to which a clock line 181 is also connected, on which relatively low frequency clock pulses are supplied.

The data stream supplied on line 179 consists of an N bit print pattern applied to each chip of the print head, where N is the number of channels to which the chip is connected. The N bits determine in one cycle which of the channels of the even numbered channel group are to be actuated, and in a subsequent cycle which of the channels of the odd numbered channel group are to be actuated. The N bit data stream additionally contains data subgroups n relating to the print state of channels of the same group, such as those selected to be actuated upon actuation on different sides of each of the selected channels. The data groups n may be 4 bit words, in which case they give the print state of two channels of the same group as the selected channels on each side of each channel selected for actuation. When the data groups n are in the form of 6-bit words, they indicate the pressure state of three channels on each side of each channel to be actuated.

At the end of printing a print line and before the next pulse on line 181 is applied to signal generator 100, data N with its subsets n are loaded into registers 173 through 177 at the rate determined by the clock pulses on line 180, typically about 10 MHz, and the data sets n are applied to a look-up table in a ROM (not shown) which applies digital signals determined by the data sets n to registers 173 through 177, which signals are then stored in the registers and be used to provide a count of pulses on line 180 which determines the charge level of the capacitors of each activated channel.

The voltage cycles applied by signal generator 100 to buses 102 and 103 are initiated by the pulses on clock line 181, and upon initiation of such a cycle, the data stored in registers 171 to 177 selects for printing the channels of one of the channel groups whose transistors 123 to 127 are on and whose transistors 143 to 147 are off, so that charging of the capacitors of the selected channels begins and is terminated by turning off the transistors 123 to 127 of the selected channels when the applied voltage level reaches a value determined by the signals stored in registers 173 to 179 and supplied from the lookup table. The registers of each of the end channels of modules forming the print head receive from the ROM sets of bits N which establish the print state of adjacent channels extending across the end region of the module in which the end channel in question is located and the adjacent module. The integrated circuit of Fig.2 is a Bi-C-MOS type.

Fig.4 illustrates the waveform generated by the signal generator 100 to energize the actuators 30 to 39 during successive phases of the two-phase multiplex circuit of Fig.2. The waveform consists of a charging section τ1 during which the charge on the capacitors 52 to 57 belonging to one of the channel groups gradually increases to predetermined values for each channel of the groups selected for actuation in which the capacitors are disconnected from the signal generator and remain at or substantially at their charged voltage level for a further section, the "hold" section τ2 during which the signal voltage is maintained at least at the level of the charging voltage. As As shown, the signal voltage is allowed to rise during this section and return to the charging voltage at the end of the section. After the τ2 section, the signal voltage goes to zero to allow the signal generator to be reconnected to the capacitors for the next phase of operation. Before this begins, a rapid discharge of the capacitors is effected as described below.

In the section τ1, the wall actuating electrodes of selected channels, for example the odd-numbered channels 21 to 27, are energized, causing the wall actuating members to deform from the channels in a chevron or cantilever shape as described in the pending European patent application, which is hereby incorporated by reference, due to the charging voltage and the polarization direction of the wall actuating members. However, the voltage rise rate is gradual, so that the magnitude of the acoustic waves generated in the ink channels only weakly disturbs the ink meniscuses of the ejection nozzles of the channels and is insufficient to eject ink droplets from the nozzles of the even-numbered channels adjacent to the activated even-numbered channels. The charging section τ1 exceeds the travel time of acoustic waves in the activated channels such that τ1≥L/C, where L is the channel length and C is the acoustic wave velocity in the channels.

In the holding section τ₂, ink is further sucked into the activated odd-numbered channels by the action of the acoustic waves and thereby the channel wall actuators relax outward as the amount of ink in the channels increases. After the holding section, usually also L/C, the ink pressure in the selected channels is a maximum and the capacitors of these channels are rapidly discharged, causing a rapid inward movement of the channel actuator walls which generate pressure waves in the selected channels. which causes an ink drop to be ejected from the nozzles of these channels. After filling ink into the channels from which an ink drop ejection takes place, the next operating phase is effected on selected even-numbered channels with another signal phase of the signal generator.

The operation of the drive circuit component of Fig. 2 will now be described in detail. In the idle state of the circuit, devices 143 to 147 and 153 to 157 are held in a conducting state by an internally generated logic signal applied to their gate electrodes, while devices 123 to 127 are in a non-conducting state. Now, channel 25 is one of the group of odd-numbered channels selected for activation; at the beginning of section τ1 of the signal from the signal generator initiated by a pulse on line 181, the field effect transistor 125 is rendered conductive by a logic signal from a register 175 applied to its gate and the signal at the gates of devices 145 and 155 is removed, rendering these devices non-conductive. The capacitors 54 and 55 therefore charge relatively slowly to a predetermined voltage during the portion τ1 through the field effect transistors 125 and 154 in the case of capacitor 54 and through the field effect transistors 125 and 156 in the case of capacitor 55, the predetermined voltage being determined by the signal stored in register 175 from the ROM. The actuating walls of the channel 25 move outward accordingly, causing an ink flow in the channel and because of the slow loading speed no ink droplets are ejected from the adjacent channels.

During the holding section τ₂, the logic signals at the field effect devices 125 are removed so as to enable the actuating parts from the control circuit signal.

Discharge of capacitors 54 and 55 is effected by applying a signal from register 175 after a predetermined number of pulses on line 180 to the gates of field effect transistors 145 and 155, which render bipolar transistor 135 conductive. This provides a discharge path for capacitor 54 through transistor 135 and diode 164, and for capacitor 55 through transistor 135 and to diode 166. Although both field effect transistors 145 and 155 are conductive during discharge, most of the discharge current flows through transistor 135 because of the relative resistances of bipolar transistor 135 and field effect transistor 155.

Note that the discharge currents of capacitors 54 and 55 flow through transistor 135 and are then equally divided between diodes 164 and 166; these relatively high discharge currents flow along the clockwise and counterclockwise paths so that their electromagnetic effects effectively cancel each other out, thereby minimizing radio frequency interference. The heating effect of current in circuit 101 is largely limited to the capacitor discharge currents and hence to the turn-on time of the bipolar transistors, which is typically 30ns. Also, discharging capacitors 54 and 55 typically takes 2us, typically resulting in currents on the order of 100mA, resulting in a rapid return of the actuating walls of channel 25 to their relaxed positions, thereby developing an ink drop ejection pressure in channel 25. Similar discharges in all odd-numbered channels which have been operated in the same operating phase take place at the same time as the discharging of capacitors 54 and 55. In the next operating cycle, the same waveform is applied to the electrodes of the walls of the even-numbered channels, which provide a operation have been selected.

Fig.3 shows part of an alternative design of a two-phase multiplex circuit to that of Fig.2 and is a C-MOS version. In the parallel paths 114, 115, 116 the diodes now shunt the corresponding field effect transistors 194, 195 and 196. The logic signals required to operate the circuit are the same as in the circuit of Fig.2 and are therefore not shown.

In the idle state, devices 124 to 126 are in a non-conductive state, and devices 194 to 196 are maintained in a conductive state by a logic signal applied to their gate electrodes.

In the first phase of operation of the circuit of Fig.3, when channel 25 is selected as one of the odd numbered channels for activation, capacitors 54 and 55 are charged during section 11 by means of a logic signal applied to the gate of field effect transistor 125 from the associated register, for example from register 175 of Fig.2, and the signal at the gate of device 195 is removed. At the end of a section determined by the signal from ROM stored in the associated register, the logic signal at the gate of device 125 is removed to terminate charging of capacitors 54 and 55 to a level determined by the pressure state of channels on different sides of channel 25 which belong to the same group as channel 25, and after section τ₂ a logic signal is applied to the gate electrode of the device 195 to make this device conductive and thereby discharge the capacitors 54 and 55. Thus, this circuit has the same advantageous features as those listed in connection with the circuit of Fig. 2.

An inkjet printhead having lead wires and drive circuits constructed and operated according to the principles described above provides the following advantages:

1. Each pusher or actuating wall participates in the operation of the channels on both sides in alternate channels. Each channel is limited by the two active walls at its edge. Each actuating wall is activated twice during the operation of each droplet printing line. This design therefore efficiently uses the piezoelectric actuating parts.

2. The connecting paths or tracks connecting the drive circuit to the actuators have a density/compactness of one track per ink channel, despite the fact that the two actuators operating each channel have three drive paths that are respectively connected to operate them. Thus, for example, channel 25 is connected to the drive circuit via a line/track 75, but the actuator walls of this channel require tracks/lines 74, 75 and 76 to operate them.

3. The high currents (100mA) generated by discharging the wall actuators only flow in a localized loop in the printhead. Very little of the heat dissipated by this current is generated in the chip, only that which arises during the switching period of the discharge transistor.

4. There is no common ground circuit in which discharge currents accumulate after discharge of the piezoelectric actuators. In circuits in which pulsed (drive or discharge) currents are conducted in a common feedback loop, which are shared in conventional inkjet drive systems, circuits must be designed to handle very significant currents (64 or 128 x 100mA). Such current values bring a risk of burnout or failure if used frequently.

5. The discharge currents flow back and forth in parallel paths arranged close to each other in dipole pairs, in which the magnetic fields of discharge currents thus essentially cancel each other out. This greatly reduces the amount of magnetic radiation to be expected compared to that generated in the common earth return line.

6. Each channel in both even and odd groups is driven by signal voltages of the same polarity, which can be selected according to the polarity direction of the ceramics in the piezoelectric actuators. A drive chip with a single polarity of drive circuits consists of p-type components and is cheaper to construct than a bipolar chip, which requires both p- and n-type components.

7. The voltage signal with which each channel is operated is compensated, which is responsible for the pressure state of channels on both sides.

It will be understood by those skilled in the art that the switching devices of the integrated circuit could include silicon controlled rectifiers, four-layer diodes or other forms of semiconductor switching devices instead of field effect and bipolar transistors.

Furthermore, it will be apparent to those skilled in the art that both the embodiments of the invention described with reference to Figs. 1, 2 and 3 and Figs. 1, 3 and 4 require that the printhead channels be arranged in two groups of nested channels, with the channels of one group alternating with those of the other group, and it is quite possible to use arrangements with more than two channel groups. Consequently, in an arrangement in which there are, for example, three groups of interconnected channels, the circuits described would have three phases of operation in which selected channels of the respective groups would be operated, rather than the two phases of operation described with respect to the circuits of Figs. 2 and 3, and there would thus be at least two inactive channels between any two simultaneously operated channels. For a given channel density, the greater the number of groups, the less acute the cross-coupling problem becomes. However, the time required to print a line of print increases and this complicates printhead design because of the need to spatially offset the nozzles of each group from those of the other group. At the highest density of channels likely to be achievable, it can be imagined that wall compliance will require that cross-coupling be limited both by grouping channels and by compensating the charging voltage of the channel capacitors depending on the printing state of adjacent channels.

Claims (17)

1.Multiplex circuit for effecting, in successive phases of operation, actuation of selected devices of different groups of devices of a series of capacitively actuated devices (23 to 27), characterized in that the circuit comprises a series of parallel electrical paths (113 to 117) by which the respective devices (23 to 27) can be connected, the paths being used to supply to a signal generator (100) two capacitors (54, 55) of each device (25) connected between the path (115) of the associated device and the respective paths (114, 116) on different sides of said path of the associated device, and first (125) and second switching means (135) arranged in each path (115) and used to be closed by correspondingly applied logic signals, so that when the first and second switching means (125, 135) of one path (115) are closed and open, respectively, and the first (124, 126) and the second switching means (134, 136) of each of the paths (114, 116) on respective different sides of said one path (115) are open and closed, respectively, a charging of the capacitors (54, 55) connected to said one path (115) takes place, and when thereafter the first and second switching means (125, 135) of said one path (115) are open and closed, respectively, a discharging of the capacitors (54, 55) connected to said one path takes place. 2. A multiplexing circuit as claimed in claim 1, characterized in that the devices (23 to 27) of the series of devices are arranged in two groups of nested devices. 3. Multiplex circuit as claimed in claim 2, characterized in that the devices (23 to 24) of a first group alternate in series with corresponding devices of a second group. 4. A circuit as claimed in any preceding claim, characterized in that a diode (165) is connected in parallel with the second switching means (135) of each path, and provides a conductive path for discharging capacitors (54, 55) connected between the path into which the diode is connected and the paths on opposite sides thereof. 5. A circuit as claimed in any preceding claim, characterized in that the first and second switching means (125, 135) are provided on a silicon chip integrated circuit, the switching means comprising transistor switches. 6. Circuit as claimed in claim 5, characterized in that the transistor switches comprise field effect transistors (125, 195). 7. A circuit as claimed in any preceding claim, characterized in that the second switching means (135, 145, 155) of each path comprises first and second switching components, of which the first switching component (155) forms a bypass path parallel to the second switching component (135, 145) during charging of the capacitors (54, 55) connected between the path (115) containing the second switching means, and the paths (114, 116) on opposite sides thereof are switched by means of the first switching means (124, 126) in the paths on the opposite sides of the path containing the second switching means, while the second switching component (135, 145) provides a conductive path for discharging the capacitors (54, 55) connected to the path (115) containing the second switching component after charging them by means of the first switching means (125) contained in the same path (115) as the second switching component. 8. Circuit according to claim 7, characterized in that the first and second switching means are provided on an integrated silicon chip circuit, the first switching means (125) comprising a field effect transistor and the first and second switching components of the second switching means comprising a field effect transistor (155) and a field effect transistor (154), respectively, which control the conductivity of a bipolar transistor (135). 9. A circuit as claimed in any preceding claim, characterized in that in each phase of operation the capacitors (52 to 57) connected to devices selected for actuation are charged in an initial portion of a voltage waveform supplied by the signal generator after the signal generator (100) is disconnected from the circuit for a further interval of the waveform prior to discharging the charged capacitors. 10. Circuit as claimed in any preceding claim, characterized in that the signal generator (100) and the parallel electrical paths (113 to 117) and their first and second switching means (125, 135, 145, 155) are formed on a silicon chip integrated circuit. 11. A circuit as claimed in any one of claims 1 to 10, characterized in that logic signal applying means (173 to 177) are provided to effect switching into and out of conduction of the first and second switching means. 12. A circuit as claimed in claim 11, characterized in that the logic signal supplying means are used to apply signals to the first and second switching means to enable charging of the capacitors of each of the devices selected for actuation, for a period of time which depends on the actuation or non-actuation state of devices adjacent to each of the selected devices. 13.Electrically pulsed apparatus comprising a multi-channel device for applying liquid droplets to a surface, a droplet application head (12) formed of electrically active material, a plurality of channels (20 to 28) for liquid formed in the head and arranged in a number of groups, nozzles communicating with respective channels, longitudinal channel side walls (30 to 39) each serving to separate one channel from the next, and electrically operable means for causing transverse displacement in opposite directions to the longitudinal side walls of each channel, the electrically operable means comprising electrodes (40 to 48) in each channel on respective opposite surfaces of the longitudinal channel side walls (30 to 39), conductive means (70 to 78) connecting the electrodes in each channel, the electrodes and the longitudinal channel side walls forming a series of capacitors (50 to 58), each consisting of one of said longitudinal channel side walls and the electrodes on the opposite sides, and a multiplex circuit to cause actuation of the longitudinal channel walls of selected channels in the respective channel groups in successive phases of operation, the circuit comprising a series of parallel electrical paths (113 to 117), the capacitors (50 to 58) being connected between successive paths of said electrical paths, a signal generator (100) connected in parallel with the parallel electrical paths, first (125) and second (135) switching means arranged in each of said paths (115), and logic signal applying means (173 to 177) to cause conduction of the first and second switching means so that when the first and second switching means (125, 135) of a path (115) are closed or open, respectively, and the first (124, 126) and second switching means (134, 136) of each of the paths (114, 116) are on different sides of the a said path (115) are open or closed, respectively, a charging of the capacitors (54, 55) connected to said one path takes place, and when thereafter the first (125) and the second switching means (135) of said one path are open or closed, respectively, a discharging of the capacitors takes place. 14. Device as claimed in claim 13, characterized in that the channels (20 to 21) are arranged in a number of groups of nested channels. 15. Device as claimed in claim 14, characterized in that the channels (20 to 28) are provided in two groups, and the channels of a first of said two groups alternate with the respective channels of a second group of said groups. 16. Device as claimed in any one of claims 13 to 15, characterized in that the signal generator (100) during charging of the capacitors (50 to 58) is used to apply a signal to the capacitors of the selected channels having a relatively slowly rising voltage, and the logic signal applying means (173 to 177) is used to cause the signal generator to be disconnected from the capacitors of the selected channels when a predetermined charging voltage is reached and, after an interval for operating the switching means, to cause a rapid discharging of the charged capacitors, whereby during charging of the capacitors of the selected channels the longitudinal side walls of said channels are displaced relatively slowly outwards and during discharging of the capacitors the channel walls are rapidly returned. 17. Apparatus as claimed in any one of claims 13 to 16, characterized in that the logic signal applying means (173 to 177) are used to apply signals to the first and second switching means in each of said parallel paths in which the capacitors of selected channels are connected to enable charging of the capacitors of each selected channel for a period of time to provide a voltage level dependent on the selected or non-selected state of adjacent channels and the group containing the selected channels.