DE68918101D1 - Speicher mit Seitenmodus. - Google Patents

Speicher mit Seitenmodus.

Info

Publication number
DE68918101D1
DE68918101D1 DE68918101T DE68918101T DE68918101D1 DE 68918101 D1 DE68918101 D1 DE 68918101D1 DE 68918101 T DE68918101 T DE 68918101T DE 68918101 T DE68918101 T DE 68918101T DE 68918101 D1 DE68918101 D1 DE 68918101D1
Authority
DE
Germany
Prior art keywords
page mode
mode memory
memory
page
mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68918101T
Other languages
English (en)
Other versions
DE68918101T2 (de
Inventor
Roderick Michael Peters West
Matthew Damian Bates
Adrian Charles Gay
Todd Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE68918101D1 publication Critical patent/DE68918101D1/de
Application granted granted Critical
Publication of DE68918101T2 publication Critical patent/DE68918101T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Dram (AREA)
DE68918101T 1989-10-12 1989-10-12 Speicher mit Seitenmodus. Expired - Fee Related DE68918101T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP19890310459 EP0422299B1 (de) 1989-10-12 1989-10-12 Speicher mit Seitenmodus

Publications (2)

Publication Number Publication Date
DE68918101D1 true DE68918101D1 (de) 1994-10-13
DE68918101T2 DE68918101T2 (de) 1995-03-30

Family

ID=8202815

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68918101T Expired - Fee Related DE68918101T2 (de) 1989-10-12 1989-10-12 Speicher mit Seitenmodus.

Country Status (3)

Country Link
EP (1) EP0422299B1 (de)
JP (1) JPH0743666B2 (de)
DE (1) DE68918101T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07240844A (ja) * 1993-03-19 1995-09-12 Mitsubishi Electric Corp 画像データ処理装置および画像データ処理方法
EP0663659A3 (de) * 1993-12-30 1995-11-22 Ibm Anzeige von Zeichen in einem Datenverarbeitungssystem.
JP3138173B2 (ja) * 1995-04-10 2001-02-26 シャープ株式会社 グラフィックス用フレームメモリ装置
DE19906382A1 (de) 1999-02-16 2000-08-24 Siemens Ag Halbleiterspeicher mit Speicherbänken
KR100472726B1 (ko) 2002-10-29 2005-03-10 주식회사 하이닉스반도체 고속 데이터억세스를 위한 반도체 메모리장치 및 그구동방법

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4396989A (en) * 1981-05-19 1983-08-02 Bell Telephone Laboratories, Incorporated Method and apparatus for providing a video display of concatenated lines and filled polygons
US4546451A (en) * 1982-02-12 1985-10-08 Metheus Corporation Raster graphics display refresh memory architecture offering rapid access speed
JPS61202394A (ja) * 1985-03-04 1986-09-08 Mitsubishi Electric Corp メモリ装置

Also Published As

Publication number Publication date
JPH03127144A (ja) 1991-05-30
EP0422299B1 (de) 1994-09-07
EP0422299A1 (de) 1991-04-17
JPH0743666B2 (ja) 1995-05-15
DE68918101T2 (de) 1995-03-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee