DE68910838D1 - Fehlererkennungsschaltung für einen Dekodierer. - Google Patents
Fehlererkennungsschaltung für einen Dekodierer.Info
- Publication number
- DE68910838D1 DE68910838D1 DE89300436T DE68910838T DE68910838D1 DE 68910838 D1 DE68910838 D1 DE 68910838D1 DE 89300436 T DE89300436 T DE 89300436T DE 68910838 T DE68910838 T DE 68910838T DE 68910838 D1 DE68910838 D1 DE 68910838D1
- Authority
- DE
- Germany
- Prior art keywords
- decoder
- detection circuit
- error detection
- error
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000001514 detection method Methods 0.000 title 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0763—Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/085—Error detection or correction by redundancy in data representation, e.g. by using checking codes using codes with inherent redundancy, e.g. n-out-of-m codes
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Logic Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63008765A JPH07120954B2 (ja) | 1988-01-18 | 1988-01-18 | デコーダのエラー検出回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE68910838D1 true DE68910838D1 (de) | 1994-01-05 |
DE68910838T2 DE68910838T2 (de) | 1994-03-17 |
Family
ID=11702007
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE89300436T Expired - Fee Related DE68910838T2 (de) | 1988-01-18 | 1989-01-18 | Fehlererkennungsschaltung für einen Dekodierer. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4949343A (de) |
EP (1) | EP0325423B1 (de) |
JP (1) | JPH07120954B2 (de) |
DE (1) | DE68910838T2 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2513514Y2 (ja) * | 1989-12-04 | 1996-10-09 | カシオ計算機株式会社 | デコ―ド回路 |
JPH03189736A (ja) * | 1989-12-19 | 1991-08-19 | Nec Corp | 選択回路の障害検出方式 |
GB9421552D0 (en) * | 1994-10-26 | 1994-12-14 | Philips Electronics Uk Ltd | Improvements in or relating to data communication |
US5995016A (en) * | 1996-12-17 | 1999-11-30 | Rambus Inc. | Method and apparatus for N choose M device selection |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3744024A (en) * | 1972-01-03 | 1973-07-03 | Stromberg Carlson Corp | Circuit for detecting the presence of other than one-bit-out-of-n bits |
US3886520A (en) * | 1974-04-03 | 1975-05-27 | Sperry Rand Corp | Checking circuit for a 1-out-of-n decoder |
US4087786A (en) * | 1976-12-08 | 1978-05-02 | Bell Telephone Laboratories, Incorporated | One-bit-out-of-N-bit checking circuit |
US4320512A (en) * | 1980-06-23 | 1982-03-16 | The Bendix Corporation | Monitored digital system |
US4380813A (en) * | 1981-04-01 | 1983-04-19 | International Business Machines Corp. | Error checking of mutually-exclusive control signals |
-
1988
- 1988-01-18 JP JP63008765A patent/JPH07120954B2/ja not_active Expired - Lifetime
-
1989
- 1989-01-18 DE DE89300436T patent/DE68910838T2/de not_active Expired - Fee Related
- 1989-01-18 EP EP89300436A patent/EP0325423B1/de not_active Expired - Lifetime
- 1989-01-18 US US07/298,369 patent/US4949343A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE68910838T2 (de) | 1994-03-17 |
EP0325423B1 (de) | 1993-11-24 |
EP0325423A2 (de) | 1989-07-26 |
JPH07120954B2 (ja) | 1995-12-20 |
US4949343A (en) | 1990-08-14 |
EP0325423A3 (en) | 1990-03-21 |
JPH01183919A (ja) | 1989-07-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |