DE60303468D1 - Fehlertolerante Vorrichtung zur Informationsverarbeitung - Google Patents

Fehlertolerante Vorrichtung zur Informationsverarbeitung

Info

Publication number
DE60303468D1
DE60303468D1 DE60303468T DE60303468T DE60303468D1 DE 60303468 D1 DE60303468 D1 DE 60303468D1 DE 60303468 T DE60303468 T DE 60303468T DE 60303468 T DE60303468 T DE 60303468T DE 60303468 D1 DE60303468 D1 DE 60303468D1
Authority
DE
Germany
Prior art keywords
information processing
processing device
fault tolerant
tolerant information
fault
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60303468T
Other languages
English (en)
Other versions
DE60303468T2 (de
Inventor
Shigeyuki Aino
Shigeo Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE60303468D1 publication Critical patent/DE60303468D1/de
Publication of DE60303468T2 publication Critical patent/DE60303468T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0712—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a virtual computing platform, e.g. logically partitioned systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Hardware Redundancy (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
DE60303468T 2002-07-10 2003-07-10 Fehlertolerante Vorrichtung zur Informationsverarbeitung Expired - Fee Related DE60303468T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002201796 2002-07-10
JP2002201796A JP2004046455A (ja) 2002-07-10 2002-07-10 情報処理装置

Publications (2)

Publication Number Publication Date
DE60303468D1 true DE60303468D1 (de) 2006-04-20
DE60303468T2 DE60303468T2 (de) 2006-09-28

Family

ID=29728480

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60303468T Expired - Fee Related DE60303468T2 (de) 2002-07-10 2003-07-10 Fehlertolerante Vorrichtung zur Informationsverarbeitung

Country Status (10)

Country Link
US (1) US20040153731A1 (de)
EP (1) EP1380950B1 (de)
JP (1) JP2004046455A (de)
KR (1) KR100566340B1 (de)
CN (1) CN1269040C (de)
AU (1) AU2003211183A1 (de)
CA (1) CA2434290A1 (de)
DE (1) DE60303468T2 (de)
ES (1) ES2253613T3 (de)
TW (1) TWI241479B (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7155721B2 (en) * 2002-06-28 2006-12-26 Hewlett-Packard Development Company, L.P. Method and apparatus for communicating information between lock stepped processors
US7085959B2 (en) * 2002-07-03 2006-08-01 Hewlett-Packard Development Company, L.P. Method and apparatus for recovery from loss of lock step
JP2004046599A (ja) * 2002-07-12 2004-02-12 Nec Corp フォルトトレラントコンピュータ装置、その再同期化方法及び再同期化プログラム
US7350026B2 (en) * 2004-12-03 2008-03-25 Thales Memory based cross compare for cross checked systems
JP4161276B2 (ja) 2004-12-17 2008-10-08 日本電気株式会社 フォルトトレラントコンピュータ装置およびその同期化方法
JP4117684B2 (ja) * 2004-12-20 2008-07-16 日本電気株式会社 フォルトトレラント・二重化コンピュータシステムとその制御方法
JP2006178636A (ja) * 2004-12-21 2006-07-06 Nec Corp フォールトトレラントコンピュータ、およびその制御方法
US7730350B2 (en) * 2005-04-28 2010-06-01 Hewlett-Packard Development Company, L.P. Method and system of determining the execution point of programs executed in lock step
US7496786B2 (en) * 2006-01-10 2009-02-24 Stratus Technologies Bermuda Ltd. Systems and methods for maintaining lock step operation
TWI397820B (zh) * 2007-03-25 2013-06-01 Mstar Semiconductor Inc 記憶體界面裝置與應用於其上之記憶體資料存取方法
US7979746B2 (en) * 2009-04-27 2011-07-12 Honeywell International Inc. Dual-dual lockstep processor assemblies and modules
JP6084366B2 (ja) * 2012-03-30 2017-02-22 沖電気工業株式会社 冗長化構築システム及び冗長化構築プログラム
JP6007822B2 (ja) * 2013-02-15 2016-10-12 日本電気株式会社 フォールトトレラントサーバ、およびそのメモリコピー方法
CN104516840B (zh) * 2013-09-29 2017-08-29 联想(北京)有限公司 信息处理方法和信息处理设备
CN112767332B (zh) * 2021-01-08 2024-05-17 心医国际数字医疗系统(大连)有限公司 一种基于cta影像的血管区域判断方法及系统

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US4394745A (en) * 1980-04-11 1983-07-19 Sony Corporation Video editing apparatus
DE3923872A1 (de) * 1989-07-19 1991-01-24 Philips Patentverwaltung Schaltungsanordnung zum steuern des zugriffs auf einen speicher
JP2836637B2 (ja) * 1990-07-06 1998-12-14 三菱電機株式会社 無線通信機の制御装置
US5249188A (en) * 1991-08-26 1993-09-28 Ag Communication Systems Corporation Synchronizing two processors as an integral part of fault detection
DE69435090T2 (de) * 1993-12-01 2009-06-10 Marathon Technologies Corp., Stow Rechnersystem mit Steuereinheiten und Rechnerelementen
FR2737029B1 (fr) * 1995-07-19 1997-09-26 Sextant Avionique Dispositif d'interface entre un calculateur a architecture redondante et un moyen de communication
DE19626184C2 (de) * 1996-06-29 1998-07-30 Alexander Ernst Erdwin Lahmann Vorrichtung zum Betreiben eines Systems mit zwei funktionsmäßig in einem Rechner parallel geschalteten Prozessoren
US5799022A (en) * 1996-07-01 1998-08-25 Sun Microsystems, Inc. Faulty module location in a fault tolerant computer system
US5953742A (en) * 1996-07-01 1999-09-14 Sun Microsystems, Inc. Memory management in fault tolerant computer systems utilizing a first and second recording mechanism and a reintegration mechanism
US5903717A (en) * 1997-04-02 1999-05-11 General Dynamics Information Systems, Inc. Fault tolerant computer system
US6314525B1 (en) * 1997-05-13 2001-11-06 3Com Corporation Means for allowing two or more network interface controller cards to appear as one card to an operating system
US6249828B1 (en) * 1997-05-13 2001-06-19 Micron Electronics, Inc. Method for the hot swap of a mass storage adapter on a system including a statically loaded adapter driver
US6065102A (en) * 1997-09-12 2000-05-16 Adaptec, Inc. Fault tolerant multiple client memory arbitration system capable of operating multiple configuration types
EP1029267B1 (de) * 1997-11-14 2002-03-27 Marathon Technologies Corporation Verfahren zur erhaltung von synchronisierter ausführung bei fehler-betriebssicheren/ fehlertoleranten rechnersystemen
US6243829B1 (en) * 1998-05-27 2001-06-05 Hewlett-Packard Company Memory controller supporting redundant synchronous memories
US6260159B1 (en) * 1998-06-15 2001-07-10 Sun Microsystems, Inc. Tracking memory page modification in a bridge for a multi-processor system
US7007190B1 (en) * 2000-09-06 2006-02-28 Cisco Technology, Inc. Data replication for redundant network components
GB2369692B (en) * 2000-11-29 2002-10-16 Sun Microsystems Inc Processor state reintegration
US6928583B2 (en) * 2001-04-11 2005-08-09 Stratus Technologies Bermuda Ltd. Apparatus and method for two computing elements in a fault-tolerant server to execute instructions in lockstep
US6970392B1 (en) * 2001-06-29 2005-11-29 Cypress Semiconductor Corp. High speed asynchronous and programmable state machine for generating almost full synchronous flags in a synchronous FIFO
US7472230B2 (en) * 2001-09-14 2008-12-30 Hewlett-Packard Development Company, L.P. Preemptive write back controller
US7085955B2 (en) * 2001-09-14 2006-08-01 Hewlett-Packard Development Company, L.P. Checkpointing with a write back controller
US6941493B2 (en) * 2002-02-27 2005-09-06 Sun Microsystems, Inc. Memory subsystem including an error detection mechanism for address and control signals
US20030163769A1 (en) * 2002-02-27 2003-08-28 Sun Microsystems, Inc. Memory module including an error detection mechanism for address and control signals
US7003692B1 (en) * 2002-05-24 2006-02-21 Cisco Technology, Inc. Dynamic configuration synchronization in support of a “hot” standby stateful switchover
US7003691B2 (en) * 2002-06-28 2006-02-21 Hewlett-Packard Development Company, L.P. Method and apparatus for seeding differences in lock-stepped processors

Also Published As

Publication number Publication date
TWI241479B (en) 2005-10-11
DE60303468T2 (de) 2006-09-28
US20040153731A1 (en) 2004-08-05
ES2253613T3 (es) 2006-06-01
KR20040005684A (ko) 2004-01-16
JP2004046455A (ja) 2004-02-12
CA2434290A1 (en) 2004-01-10
TW200402622A (en) 2004-02-16
AU2003211183A1 (en) 2004-01-29
CN1269040C (zh) 2006-08-09
EP1380950A1 (de) 2004-01-14
KR100566340B1 (ko) 2006-03-31
EP1380950B1 (de) 2006-02-08
CN1472650A (zh) 2004-02-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee