DE60302809D1 - Vorrichtung und Verfahren zur selektiven Steuerung der Speicherattribute - Google Patents

Vorrichtung und Verfahren zur selektiven Steuerung der Speicherattribute

Info

Publication number
DE60302809D1
DE60302809D1 DE60302809T DE60302809T DE60302809D1 DE 60302809 D1 DE60302809 D1 DE 60302809D1 DE 60302809 T DE60302809 T DE 60302809T DE 60302809 T DE60302809 T DE 60302809T DE 60302809 D1 DE60302809 D1 DE 60302809D1
Authority
DE
Germany
Prior art keywords
selectively controlling
controlling memory
memory attributes
attributes
selectively
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60302809T
Other languages
English (en)
Other versions
DE60302809T2 (de
Inventor
G Glenn Henry
Terry Parks
Rodney E Hooker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IP First LLC
Original Assignee
IP First LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IP First LLC filed Critical IP First LLC
Application granted granted Critical
Publication of DE60302809D1 publication Critical patent/DE60302809D1/de
Publication of DE60302809T2 publication Critical patent/DE60302809T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
DE60302809T 2002-02-19 2003-02-18 Vorrichtung und Verfahren zur selektiven Steuerung der Speicherattribute Expired - Lifetime DE60302809T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US227572 1981-01-22
US35824202P 2002-02-19 2002-02-19
US358242 2002-02-19
US10/227,572 US7315921B2 (en) 2002-02-19 2002-08-22 Apparatus and method for selective memory attribute control

Publications (2)

Publication Number Publication Date
DE60302809D1 true DE60302809D1 (de) 2006-01-26
DE60302809T2 DE60302809T2 (de) 2006-06-29

Family

ID=27737099

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60302809T Expired - Lifetime DE60302809T2 (de) 2002-02-19 2003-02-18 Vorrichtung und Verfahren zur selektiven Steuerung der Speicherattribute

Country Status (3)

Country Link
US (1) US7315921B2 (de)
EP (1) EP1336918B1 (de)
DE (1) DE60302809T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7181596B2 (en) * 2002-02-12 2007-02-20 Ip-First, Llc Apparatus and method for extending a microprocessor instruction set
US7328328B2 (en) * 2002-02-19 2008-02-05 Ip-First, Llc Non-temporal memory reference control mechanism
US7155598B2 (en) * 2002-04-02 2006-12-26 Ip-First, Llc Apparatus and method for conditional instruction execution
US7373483B2 (en) * 2002-04-02 2008-05-13 Ip-First, Llc Mechanism for extending the number of registers in a microprocessor
US7185180B2 (en) * 2002-04-02 2007-02-27 Ip-First, Llc Apparatus and method for selective control of condition code write back
US7302551B2 (en) * 2002-04-02 2007-11-27 Ip-First, Llc Suppression of store checking
US7380103B2 (en) 2002-04-02 2008-05-27 Ip-First, Llc Apparatus and method for selective control of results write back
US20040111529A1 (en) * 2002-12-10 2004-06-10 Intel Corporation (A Delaware Corporation) Dynamic host based load balancing of a multihomed network
US20050278517A1 (en) 2004-05-19 2005-12-15 Kar-Lik Wong Systems and methods for performing branch prediction in a variable length instruction set microprocessor
WO2007049150A2 (en) 2005-09-28 2007-05-03 Arc International (Uk) Limited Architecture for microprocessor-based systems including simd processing unit and associated systems and methods
US10656945B2 (en) 2012-06-15 2020-05-19 International Business Machines Corporation Next instruction access intent instruction for indicating usage of a storage operand by one or more instructions subsequent to a next sequential instruction
US20170192788A1 (en) * 2016-01-05 2017-07-06 Intel Corporation Binary translation support using processor instruction prefixes
US10908915B1 (en) * 2019-07-31 2021-02-02 Micron Technology, Inc. Extended tags for speculative and normal executions
US11194582B2 (en) 2019-07-31 2021-12-07 Micron Technology, Inc. Cache systems for main and speculative threads of processors
US11200166B2 (en) 2019-07-31 2021-12-14 Micron Technology, Inc. Data defined caches for speculative and normal executions
US11048636B2 (en) 2019-07-31 2021-06-29 Micron Technology, Inc. Cache with set associativity having data defined cache sets
US11010288B2 (en) 2019-07-31 2021-05-18 Micron Technology, Inc. Spare cache set to accelerate speculative execution, wherein the spare cache set, allocated when transitioning from non-speculative execution to speculative execution, is reserved during previous transitioning from the non-speculative execution to the speculative execution
US10915326B1 (en) 2019-07-31 2021-02-09 Micron Technology, Inc. Cache systems and circuits for syncing caches or cache sets

Family Cites Families (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US521872A (en) * 1894-06-26 Clamp
US3657705A (en) 1969-11-12 1972-04-18 Honeywell Inc Instruction translation control with extended address prefix decoding
US4064554A (en) 1976-08-16 1977-12-20 Texas Instruments Incorporated Microcomputer with code conversion
US4217638A (en) 1977-05-19 1980-08-12 Tokyo Shibaura Electric Co., Ltd. Data-processing apparatus and method
JPS57157362A (en) 1981-03-25 1982-09-28 Hitachi Ltd Method and apparatus of execution path career data pickup for architecture program
US4547849A (en) 1981-12-09 1985-10-15 Glenn Louie Interface between a microprocessor and a coprocessor
JPS6491228A (en) 1987-09-30 1989-04-10 Takeshi Sakamura Data processor
US5218712A (en) 1987-07-01 1993-06-08 Digital Equipment Corporation Providing a data processor with a user-mode accessible mode of operations in which the processor performs processing operations without interruption
US5448744A (en) 1989-11-06 1995-09-05 Motorola, Inc. Integrated circuit microprocessor with programmable chip select logic
JPH04306735A (ja) 1991-04-04 1992-10-29 Toshiba Corp 非同期割込み禁止機構
EP0550289A3 (en) 1992-01-02 1993-11-10 Amdahl Corp A mechanism to detect stores into the instruction stream
JP3644959B2 (ja) 1992-09-29 2005-05-11 セイコーエプソン株式会社 マイクロプロセッサシステム
DE69427265T2 (de) 1993-10-29 2002-05-02 Advanced Micro Devices Inc Superskalarbefehlsdekoder
US5481684A (en) 1994-01-11 1996-01-02 Exponential Technology, Inc. Emulating operating system calls in an alternate instruction set using a modified code segment descriptor
US5687338A (en) 1994-03-01 1997-11-11 Intel Corporation Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor
ZA954460B (en) 1994-09-30 1996-02-05 Intel Corp Method and apparatus for processing memory-type information within a microprocessor
KR100374803B1 (ko) 1995-05-25 2003-05-12 삼성전자주식회사 튜닝포크형자이로스코프
US5822778A (en) 1995-06-07 1998-10-13 Advanced Micro Devices, Inc. Microprocessor and method of using a segment override prefix instruction field to expand the register file
US5768574A (en) 1995-06-07 1998-06-16 Advanced Micro Devices, Inc. Microprocessor using an instruction field to expand the condition flags and a computer system employing the microprocessor
WO1997022922A1 (en) 1995-12-15 1997-06-26 Intel Corporation Instruction encoding techniques for microcontroller architecture
US5826089A (en) 1996-01-04 1998-10-20 Advanced Micro Devices, Inc. Instruction translation unit configured to translate from a first instruction set to a second instruction set
JP3663710B2 (ja) 1996-01-17 2005-06-22 ヤマハ株式会社 プログラムの生成方法およびプロセッサの割込制御方法
US5857103A (en) 1996-06-14 1999-01-05 Sun Microsystems, Inc. Method and apparatus for addressing extended registers on a processor in a computer system
US5778220A (en) 1996-11-18 1998-07-07 Intel Corporation Method and apparatus for disabling interrupts in a highly pipelined processor
JPH10161871A (ja) 1996-11-28 1998-06-19 Toshiba Corp プロセッサ
US5937199A (en) 1997-06-03 1999-08-10 International Business Machines Corporation User programmable interrupt mask with timeout for enhanced resource locking efficiency
US5875342A (en) 1997-06-03 1999-02-23 International Business Machines Corporation User programmable interrupt mask with timeout
US6058472A (en) 1997-06-25 2000-05-02 Sun Microsystems, Inc. Apparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machine
US5913049A (en) 1997-07-31 1999-06-15 Texas Instruments Incorporated Multi-stream complex instruction set microprocessor
US6230259B1 (en) 1997-10-31 2001-05-08 Advanced Micro Devices, Inc. Transparent extended state save
US6157996A (en) 1997-11-13 2000-12-05 Advanced Micro Devices, Inc. Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space
EP0942359B1 (de) 1998-02-19 2012-07-04 Lantiq Deutschland GmbH Vorrichtung zur Ausführung von Programmbefehlen
EP0942357A3 (de) * 1998-03-11 2000-03-22 Matsushita Electric Industrial Co., Ltd. Mit einer Mehrzahl von Befehlsformaten vereinbarer Datenprozessor
US6085312A (en) 1998-03-31 2000-07-04 Intel Corporation Method and apparatus for handling imprecise exceptions
US6356270B2 (en) 1998-03-31 2002-03-12 Intel Corporation Efficient utilization of write-combining buffers
US6014735A (en) 1998-03-31 2000-01-11 Intel Corporation Instruction set extension using prefixes
US6581154B1 (en) 1999-02-17 2003-06-17 Intel Corporation Expanding microcode associated with full and partial width macroinstructions
US6351806B1 (en) * 1999-10-06 2002-02-26 Cradle Technologies Risc processor using register codes for expanded instruction set
US6456891B1 (en) 1999-10-27 2002-09-24 Advanced Micro Devices, Inc. System and method for transparent handling of extended register states
JP3669884B2 (ja) * 1999-11-11 2005-07-13 富士通株式会社 処理装置
US6560694B1 (en) 2000-01-14 2003-05-06 Advanced Micro Devices, Inc. Double prefix overrides to provide 16-bit operand size in a 32/64 operating mode
JP2002175261A (ja) 2000-12-05 2002-06-21 Oki Electric Ind Co Ltd データ転送制御回路
US7181596B2 (en) 2002-02-12 2007-02-20 Ip-First, Llc Apparatus and method for extending a microprocessor instruction set
US7529912B2 (en) 2002-02-12 2009-05-05 Via Technologies, Inc. Apparatus and method for instruction-level specification of floating point format
US7328328B2 (en) 2002-02-19 2008-02-05 Ip-First, Llc Non-temporal memory reference control mechanism
US6823414B2 (en) 2002-03-01 2004-11-23 Intel Corporation Interrupt disabling apparatus, system, and method
US7395412B2 (en) 2002-03-08 2008-07-01 Ip-First, Llc Apparatus and method for extending data modes in a microprocessor
US7373483B2 (en) 2002-04-02 2008-05-13 Ip-First, Llc Mechanism for extending the number of registers in a microprocessor
TWI282066B (en) 2002-08-22 2007-06-01 Ip First Llc Apparatus and method for extending data modes in a microprocessor

Also Published As

Publication number Publication date
EP1336918A3 (de) 2004-08-11
US20030159009A1 (en) 2003-08-21
DE60302809T2 (de) 2006-06-29
US7315921B2 (en) 2008-01-01
EP1336918A2 (de) 2003-08-20
EP1336918B1 (de) 2005-12-21

Similar Documents

Publication Publication Date Title
DE60214971D1 (de) Verfahren und Vorrichtung zur Steuerung von Geräten
DE602004030979D1 (de) Verfahren und Vorrichtung zur Kontrolle der Paketpriorität
DE60212744D1 (de) Vorrichtung zur Steuerung der Spannungsversorgung und zugehöriges Verfahren
ATE462285T1 (de) Vorrichtung und verfahren zur zentralen steuerung von mesh-netzwerken
DE60331013D1 (de) Vorrichtung und Verfahren zur Fahrzeugantriebssteuerung
DE10393837B8 (de) Verfahren und Vorrichtung zur Beheizung von Schmelzen
DE502004006796D1 (de) Verfahren und vorrichtung zur einstellung benutzerabhängiger parameterwerte
DE112004000642D2 (de) Verfahren und Vorrichtung zur Radsturzverstellung
DE60233001D1 (de) Vorrichtung und verfahren zur steuerung eines luftbetankungsschlauchs
DE60228013D1 (de) Vorrichtung und Verfahren zur Fahrzeugsteuerung
DE60318651D1 (de) Verfahren und Vorrichtung zur dynamischen Konfigurationsverwaltung
DE602005022265D1 (de) Vorrichtung und Verfahren zur Spannungsversorgungssteuerung
DE50203544D1 (de) Verfahren und Vorrichtung zur Drehbearbeitung
DE60302809D1 (de) Vorrichtung und Verfahren zur selektiven Steuerung der Speicherattribute
DE60315228D1 (de) Einrichtung und verfahren zur rückkopplungskontrolle
DE60336111D1 (de) Informationsverarbeitungsgerät und Verfahren zur Steuerung desgleichen
DE602005024986D1 (de) Verfahren und vorrichtung zur generatorsteuerung
DE60235061D1 (de) Verfahren und Vorrichtung zur synchronen Steuerung
DE60330425D1 (de) Bilderzeugungsgerät und Verfahren zur Kontrolle der Benutzung
DE10393696D2 (de) Verfahren und Vorrichtung zur Regelung der Fahrzeuglängsbestätigung
DE602004010735D1 (de) Vorrichtung und Verfahren zur Regelung der Fahrzeugbewegung
DE50109658D1 (de) Vorrichtung und Verfahren zur Sprachsteuerung
DE60323590D1 (de) Kreuztischvorrichtung und Verfahren zur Steuerung derselben
DE60212242D1 (de) Verfahren und Vorrichtung zur Steuerung der Kraftstoffeinspritzung
DE60303556D1 (de) Vorrichtung und Verfahren zur Kontrolle eines Gassacks

Legal Events

Date Code Title Description
8364 No opposition during term of opposition