DE60234394D1 - ACTIVATION OF MEMORY REDUNDANCY DURING THE TEST - Google Patents

ACTIVATION OF MEMORY REDUNDANCY DURING THE TEST

Info

Publication number
DE60234394D1
DE60234394D1 DE60234394T DE60234394T DE60234394D1 DE 60234394 D1 DE60234394 D1 DE 60234394D1 DE 60234394 T DE60234394 T DE 60234394T DE 60234394 T DE60234394 T DE 60234394T DE 60234394 D1 DE60234394 D1 DE 60234394D1
Authority
DE
Germany
Prior art keywords
activation
test
memory redundancy
redundancy during
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60234394T
Other languages
German (de)
Inventor
Michael R Ouellette
Jeremy Rowland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE60234394D1 publication Critical patent/DE60234394D1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G11C29/16—Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/702—Masking faults in memories by using spares or by reconfiguring by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0407—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals on power on
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0409—Online test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1208—Error catch memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Methods and apparatuses for enabling a dedundant memory element (20) during testing of a memory array (14).
DE60234394T 2002-12-16 2002-12-16 ACTIVATION OF MEMORY REDUNDANCY DURING THE TEST Expired - Lifetime DE60234394D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2002/040473 WO2004061852A1 (en) 2002-12-16 2002-12-16 Enabling memory redundancy during testing

Publications (1)

Publication Number Publication Date
DE60234394D1 true DE60234394D1 (en) 2009-12-24

Family

ID=32710251

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60234394T Expired - Lifetime DE60234394D1 (en) 2002-12-16 2002-12-16 ACTIVATION OF MEMORY REDUNDANCY DURING THE TEST

Country Status (8)

Country Link
EP (1) EP1620857B1 (en)
JP (1) JP4215723B2 (en)
CN (1) CN100552805C (en)
AT (1) ATE448547T1 (en)
AU (1) AU2002361765A1 (en)
DE (1) DE60234394D1 (en)
TW (1) TWI257103B (en)
WO (1) WO2004061852A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7219275B2 (en) * 2005-02-08 2007-05-15 International Business Machines Corporation Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancy
TWI409820B (en) * 2009-02-18 2013-09-21 King Yuan Electronics Co Ltd Semiconductor Test System with Self - Test for Memory Repair Analysis
CN102411994B (en) * 2011-11-24 2015-01-07 深圳市芯海科技有限公司 Data verification method and apparatus for integrated circuit built-in memory
KR102038036B1 (en) * 2013-05-28 2019-10-30 에스케이하이닉스 주식회사 Semiconductor and semiconductor system including the same
JP6706371B2 (en) * 2018-08-08 2020-06-03 シャープ株式会社 Display device and control method thereof
CN109857606A (en) * 2019-02-12 2019-06-07 深圳忆联信息系统有限公司 Avoid the memory redundant digit test method and device of loss yield
CN114267402B (en) * 2021-11-22 2022-11-18 上海芯存天下电子科技有限公司 Bad storage unit testing method, device, equipment and storage medium of flash memory

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4819205A (en) * 1985-03-25 1989-04-04 Motorola, Inc. Memory system having memory elements independently defined as being on-line or off-line
DE69626625T2 (en) * 1996-04-18 2003-10-02 St Microelectronics Srl Method for detecting redundant faulty addresses in a memory arrangement with redundancy
KR100234377B1 (en) * 1997-04-10 1999-12-15 윤종용 Redundancy memory cell control circuit and method for memory device

Also Published As

Publication number Publication date
TW200519954A (en) 2005-06-16
TWI257103B (en) 2006-06-21
AU2002361765A1 (en) 2004-07-29
WO2004061852A1 (en) 2004-07-22
CN1708808A (en) 2005-12-14
EP1620857A4 (en) 2006-08-02
EP1620857A1 (en) 2006-02-01
JP2006510156A (en) 2006-03-23
CN100552805C (en) 2009-10-21
ATE448547T1 (en) 2009-11-15
EP1620857B1 (en) 2009-11-11
JP4215723B2 (en) 2009-01-28

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Legal Events

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8320 Willingness to grant licences declared (paragraph 23)
8364 No opposition during term of opposition