DE60233168D1 - Verfahren und vorrichtung zur mehrfachverarbeitungsausführung von computeranweisungen - Google Patents

Verfahren und vorrichtung zur mehrfachverarbeitungsausführung von computeranweisungen

Info

Publication number
DE60233168D1
DE60233168D1 DE60233168T DE60233168T DE60233168D1 DE 60233168 D1 DE60233168 D1 DE 60233168D1 DE 60233168 T DE60233168 T DE 60233168T DE 60233168 T DE60233168 T DE 60233168T DE 60233168 D1 DE60233168 D1 DE 60233168D1
Authority
DE
Germany
Prior art keywords
sub
loop
processor
main processor
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60233168T
Other languages
English (en)
Inventor
Hidetaka Magoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Interactive Entertainment Inc
Original Assignee
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc filed Critical Sony Computer Entertainment Inc
Application granted granted Critical
Publication of DE60233168D1 publication Critical patent/DE60233168D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • A—HUMAN NECESSITIES
    • A63—SPORTS; GAMES; AMUSEMENTS
    • A63F—CARD, BOARD, OR ROULETTE GAMES; INDOOR GAMES USING SMALL MOVING PLAYING BODIES; VIDEO GAMES; GAMES NOT OTHERWISE PROVIDED FOR
    • A63F2300/00—Features of games using an electronically generated display having two or more dimensions, e.g. on a television screen, showing representations related to the game
    • A63F2300/20—Features of games using an electronically generated display having two or more dimensions, e.g. on a television screen, showing representations related to the game characterised by details of the game platform
    • A63F2300/203—Image generating hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
DE60233168T 2002-03-13 2002-10-18 Verfahren und vorrichtung zur mehrfachverarbeitungsausführung von computeranweisungen Expired - Lifetime DE60233168D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US36387302P 2002-03-13 2002-03-13
US10/202,355 US7162620B2 (en) 2002-03-13 2002-07-24 Methods and apparatus for multi-processing execution of computer instructions
PCT/US2002/033507 WO2003079206A1 (en) 2002-03-13 2002-10-18 Methods and apparatus for multi-processing execution of computer instructions

Publications (1)

Publication Number Publication Date
DE60233168D1 true DE60233168D1 (de) 2009-09-10

Family

ID=28044473

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60233168T Expired - Lifetime DE60233168D1 (de) 2002-03-13 2002-10-18 Verfahren und vorrichtung zur mehrfachverarbeitungsausführung von computeranweisungen

Country Status (9)

Country Link
US (1) US7162620B2 (de)
EP (1) EP1483675B1 (de)
JP (1) JP3977340B2 (de)
KR (1) KR100667509B1 (de)
AT (1) ATE438145T1 (de)
AU (1) AU2002335102A1 (de)
DE (1) DE60233168D1 (de)
ES (1) ES2330318T3 (de)
WO (1) WO2003079206A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6825843B2 (en) * 2002-07-18 2004-11-30 Nvidia Corporation Method and apparatus for loop and branch instructions in a programmable graphics pipeline
US7533382B2 (en) * 2002-10-30 2009-05-12 Stmicroelectronics, Inc. Hyperprocessor
US7218291B2 (en) * 2004-09-13 2007-05-15 Nvidia Corporation Increased scalability in the fragment shading pipeline
KR100806274B1 (ko) * 2005-12-06 2008-02-22 한국전자통신연구원 멀티 쓰레디드 프로세서 기반의 병렬 시스템을 위한 적응형실행 방법
US20090160863A1 (en) * 2007-12-21 2009-06-25 Michael Frank Unified Processor Architecture For Processing General and Graphics Workload
US8359365B2 (en) 2008-02-11 2013-01-22 Nuix Pty Ltd Systems and methods for load-balancing by secondary processors in parallel document indexing
US9928260B2 (en) 2008-02-11 2018-03-27 Nuix Pty Ltd Systems and methods for scalable delocalized information governance
US9785700B2 (en) 2008-02-11 2017-10-10 Nuix Pty Ltd Systems and methods for load-balancing by secondary processors in parallelized indexing
US8151090B2 (en) * 2009-02-17 2012-04-03 Samsung Electronics Co., Ltd. Sequentially propagating instructions of thread through serially coupled PEs for concurrent processing respective thread on different data and synchronizing upon branch
JP2012252374A (ja) * 2011-05-31 2012-12-20 Renesas Electronics Corp 情報処理装置
US9529599B2 (en) * 2012-02-13 2016-12-27 William Erik Anderson Dynamic propagation with iterative pipeline processing
JP5831316B2 (ja) * 2012-03-19 2015-12-09 富士通株式会社 並列処理装置
US10826930B2 (en) 2014-07-22 2020-11-03 Nuix Pty Ltd Systems and methods for parallelized custom data-processing and search
KR20160054850A (ko) * 2014-11-07 2016-05-17 삼성전자주식회사 다수의 프로세서들을 운용하는 장치 및 방법
US11200249B2 (en) 2015-04-16 2021-12-14 Nuix Limited Systems and methods for data indexing with user-side scripting
JP6669265B2 (ja) * 2016-09-08 2020-03-18 株式会社島津製作所 ガスクロマトグラフ

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081575A (en) * 1987-11-06 1992-01-14 Oryx Corporation Highly parallel computer architecture employing crossbar switch with selectable pipeline delay
US5522083A (en) 1989-11-17 1996-05-28 Texas Instruments Incorporated Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors
US5809340A (en) * 1993-04-30 1998-09-15 Packard Bell Nec Adaptively generating timing signals for access to various memory devices based on stored profiles
US6311286B1 (en) * 1993-04-30 2001-10-30 Nec Corporation Symmetric multiprocessing system with unified environment and distributed system functions
US6219773B1 (en) 1993-10-18 2001-04-17 Via-Cyrix, Inc. System and method of retiring misaligned write operands from a write buffer
US5838987A (en) 1995-10-06 1998-11-17 National Semiconductor Corporation Processor for eliminating external isochronous subsystems
US6088783A (en) 1996-02-16 2000-07-11 Morton; Steven G DPS having a plurality of like processors controlled in parallel by an instruction word, and a control processor also controlled by the instruction word
US5764934A (en) 1996-07-03 1998-06-09 Intel Corporation Processor subsystem for use with a universal computer architecture
EP0950216B1 (de) 1997-10-02 2003-11-26 Koninklijke Philips Electronics N.V. Vorrichtung zur ausführung virtueller maschinenbefehle
US6101592A (en) 1998-12-18 2000-08-08 Billions Of Operations Per Second, Inc. Methods and apparatus for scalable instruction set architecture with dynamic compact instructions
US6212617B1 (en) 1998-05-13 2001-04-03 Microsoft Corporation Parallel processing method and system using a lazy parallel data type to reduce inter-processor communication
US6269440B1 (en) 1999-02-05 2001-07-31 Agere Systems Guardian Corp. Accelerating vector processing using plural sequencers to process multiple loop iterations simultaneously
JP3946393B2 (ja) 1999-10-19 2007-07-18 株式会社東芝 階層構造をもつ並列計算機

Also Published As

Publication number Publication date
US20030177343A1 (en) 2003-09-18
KR20040086462A (ko) 2004-10-08
AU2002335102A1 (en) 2003-09-29
EP1483675A1 (de) 2004-12-08
JP3977340B2 (ja) 2007-09-19
ATE438145T1 (de) 2009-08-15
KR100667509B1 (ko) 2007-01-10
US7162620B2 (en) 2007-01-09
WO2003079206A1 (en) 2003-09-25
ES2330318T3 (es) 2009-12-09
EP1483675A4 (de) 2007-02-14
EP1483675B1 (de) 2009-07-29
JP2005520249A (ja) 2005-07-07

Similar Documents

Publication Publication Date Title
DE60233168D1 (de) Verfahren und vorrichtung zur mehrfachverarbeitungsausführung von computeranweisungen
ATE450000T1 (de) Verfahren und vorrichtung für die befehlssatzarchitektur mit dyadischen digitalen signalverarbeitungsbefehlen
WO2007112406A3 (en) Programming a multi-processor system
DE60044752D1 (de) Verzweigungsbefehl für einen mehrfachverarbeitungsprozessor
ATE125966T1 (de) Staffelverfahren zur ausführung von verschachtelten schleifen in mehrprozessorrechnern.
ATE498158T1 (de) Umkonfigurierbares verarbeitungssystem und - verfahren
WO2004042560A3 (en) Pipeline coprocessor
WO2004099917A3 (en) Stochastically generating facility and well schedules
GB2429554A (en) Method and apparatus to vectorize multiple input instructions
EP1124182A3 (de) Übertragung von Ergebnissen in einem Prozessor, und Verfahren zur Kompilierung
GB2427493A (en) Using results of speculative branches to predict branches during non-speculative execution
WO2006055864A3 (en) Method and apparatus for implementing task management of computer operations
DE60318494D1 (de) Verfahren, einrichtung und system zur durchführung von kalkulationsoperationen
ATE232616T1 (de) Verfahren zur überwachung des programmablaufs
DE60307532D1 (de) Paralleles Prozess-Ausführungsverfahren und Mehrprozessorenrechner
ATE415655T1 (de) Vorrichtung und verfahren zum automatischen parallelisieren von netzwerkanwendungen durch pipeline-transformation
ATE493703T1 (de) Programmierbare datenverarbeitungsschaltung, die simd-befehle unterstützt
EA200600036A1 (ru) Способ прогнозирования и автоматизированного проектирования одиночной скважины и вычислительная система для его осуществления
US8869123B2 (en) System and method for applying a sequence of operations code to program configurable logic circuitry
GB0516236D0 (en) Instructions to assist the processing of a cipher message
DE69419036D1 (de) Datenverarbeitungssystem und betriebsverfahren
ATE461480T1 (de) Verfahren und vorrichtung für befehlssatzarchitektur zur gleichzeitigen durchführung von primären und schatten- digitalsignalverarbeitungssubbefehlen
WO1999031579A3 (en) Computer instruction which generates multiple data-type results
WO2004063834A3 (en) Method and apparatus for instruction compression
ATE556372T1 (de) Übersetzung einer reihe von computeranweisungen

Legal Events

Date Code Title Description
8364 No opposition during term of opposition