DE60231191D1 - Feldprogrammierbare Vorrichtung - Google Patents

Feldprogrammierbare Vorrichtung

Info

Publication number
DE60231191D1
DE60231191D1 DE60231191T DE60231191T DE60231191D1 DE 60231191 D1 DE60231191 D1 DE 60231191D1 DE 60231191 T DE60231191 T DE 60231191T DE 60231191 T DE60231191 T DE 60231191T DE 60231191 D1 DE60231191 D1 DE 60231191D1
Authority
DE
Germany
Prior art keywords
field programmable
programmable device
field
programmable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60231191T
Other languages
English (en)
Inventor
Deepak Agarwal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sicronic Remote KG LLC
Original Assignee
Sicronic Remote KG LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sicronic Remote KG LLC filed Critical Sicronic Remote KG LLC
Application granted granted Critical
Publication of DE60231191D1 publication Critical patent/DE60231191D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
DE60231191T 2002-04-03 2002-04-03 Feldprogrammierbare Vorrichtung Expired - Lifetime DE60231191D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02252425A EP1351394B1 (de) 2002-04-03 2002-04-03 Feldprogrammierbare Vorrichtung

Publications (1)

Publication Number Publication Date
DE60231191D1 true DE60231191D1 (de) 2009-04-02

Family

ID=27838153

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60231191T Expired - Lifetime DE60231191D1 (de) 2002-04-03 2002-04-03 Feldprogrammierbare Vorrichtung

Country Status (3)

Country Link
US (1) US6870393B2 (de)
EP (2) EP2051381B1 (de)
DE (1) DE60231191D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE60204539D1 (de) * 2002-04-03 2005-07-14 Sgs Thomson Microelectronics Feldprogrammierbare Vorrichtung
US7506210B1 (en) 2003-06-26 2009-03-17 Xilinx, Inc. Method of debugging PLD configuration using boundary scan
US8566616B1 (en) * 2004-09-10 2013-10-22 Altera Corporation Method and apparatus for protecting designs in SRAM-based programmable logic devices and the like
US8612772B1 (en) 2004-09-10 2013-12-17 Altera Corporation Security core using soft key
US7480843B1 (en) * 2004-09-29 2009-01-20 Xilinx, Inc. Configuration access from a boundary-scannable device
KR20090035538A (ko) * 2006-07-27 2009-04-09 파나소닉 주식회사 반도체 집적 회로, 프로그램 변환 장치 및 매핑 장치
US10268180B2 (en) * 2010-07-28 2019-04-23 Fisher-Rosemount Systems, Inc. Handheld field maintenance tool with simulation of field device for instruction or qualification

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5909125A (en) * 1996-12-24 1999-06-01 Xilinx, Inc. FPGA using RAM control signal lines as routing or logic resources after configuration
US5910732A (en) 1997-03-12 1999-06-08 Xilinx, Inc. Programmable gate array having shared signal lines for interconnect and configuration
US6097212A (en) * 1997-10-09 2000-08-01 Lattice Semiconductor Corporation Variable grain architecture for FPGA integrated circuits

Also Published As

Publication number Publication date
EP2051381A1 (de) 2009-04-22
EP2051381B1 (de) 2011-09-14
EP1351394B1 (de) 2009-02-18
US20040017221A1 (en) 2004-01-29
US6870393B2 (en) 2005-03-22
EP1351394A1 (de) 2003-10-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition