DE60223394D1 - Verfaren und vorrichtung zum einteilen von anforderungen für einen dynamischen direktzugriffsspeicherbaustein - Google Patents

Verfaren und vorrichtung zum einteilen von anforderungen für einen dynamischen direktzugriffsspeicherbaustein

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Publication number
DE60223394D1
DE60223394D1 DE60223394T DE60223394T DE60223394D1 DE 60223394 D1 DE60223394 D1 DE 60223394D1 DE 60223394 T DE60223394 T DE 60223394T DE 60223394 T DE60223394 T DE 60223394T DE 60223394 D1 DE60223394 D1 DE 60223394D1
Authority
DE
Germany
Prior art keywords
access memory
direct access
dynamic direct
assigning
requirements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60223394T
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English (en)
Other versions
DE60223394T2 (de
Inventor
Wolf-Dietrich Weber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sonics Inc
Original Assignee
Sonics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25525212&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE60223394(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Sonics Inc filed Critical Sonics Inc
Publication of DE60223394D1 publication Critical patent/DE60223394D1/de
Application granted granted Critical
Publication of DE60223394T2 publication Critical patent/DE60223394T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
DE60223394T 2001-10-12 2002-02-21 Verfahren und vorrichtung zum einteilen von anforderungen für einen dynamischen direktzugriffsspeicherbaustein Expired - Lifetime DE60223394T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/977,510 US6961834B2 (en) 2001-10-12 2001-10-12 Method and apparatus for scheduling of requests to dynamic random access memory device
US977510 2001-10-12
PCT/US2002/005288 WO2003040927A1 (en) 2001-10-12 2002-02-21 Method and apparatus for scheduling of requests to a dynamic random access memory device

Publications (2)

Publication Number Publication Date
DE60223394D1 true DE60223394D1 (de) 2007-12-20
DE60223394T2 DE60223394T2 (de) 2008-08-28

Family

ID=25525212

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60223394T Expired - Lifetime DE60223394T2 (de) 2001-10-12 2002-02-21 Verfahren und vorrichtung zum einteilen von anforderungen für einen dynamischen direktzugriffsspeicherbaustein

Country Status (6)

Country Link
US (1) US6961834B2 (de)
EP (1) EP1435039B1 (de)
JP (1) JP4095032B2 (de)
AT (1) ATE377793T1 (de)
DE (1) DE60223394T2 (de)
WO (1) WO2003040927A1 (de)

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US7356633B2 (en) * 2002-05-03 2008-04-08 Sonics, Inc. Composing on-chip interconnects with configurable interfaces
US7194566B2 (en) * 2002-05-03 2007-03-20 Sonics, Inc. Communication system and method with configurable posting points
US7254603B2 (en) * 2002-05-03 2007-08-07 Sonics, Inc. On-chip inter-network performance optimization using configurable performance parameters
US7302691B2 (en) * 2002-05-10 2007-11-27 Sonics, Incorporated Scalable low bandwidth multicast handling in mixed core systems
US7836252B2 (en) 2002-08-29 2010-11-16 Micron Technology, Inc. System and method for optimizing interconnections of memory devices in a multichip module
US7603441B2 (en) * 2002-12-27 2009-10-13 Sonics, Inc. Method and apparatus for automatic configuration of multiple on-chip interconnects
US7827283B2 (en) * 2003-02-19 2010-11-02 International Business Machines Corporation System for managing and controlling storage access requirements
US7245145B2 (en) 2003-06-11 2007-07-17 Micron Technology, Inc. Memory module and method having improved signal routing topology
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US9087036B1 (en) 2004-08-12 2015-07-21 Sonics, Inc. Methods and apparatuses for time annotated transaction level modeling
US8504992B2 (en) * 2003-10-31 2013-08-06 Sonics, Inc. Method and apparatus for establishing a quality of service model
US7665069B2 (en) * 2003-10-31 2010-02-16 Sonics, Inc. Method and apparatus for establishing a quality of service model
US7366864B2 (en) 2004-03-08 2008-04-29 Micron Technology, Inc. Memory hub architecture having programmable lane widths
US7120723B2 (en) 2004-03-25 2006-10-10 Micron Technology, Inc. System and method for memory hub-based expansion bus
US7590797B2 (en) 2004-04-08 2009-09-15 Micron Technology, Inc. System and method for optimizing interconnections of components in a multichip memory module
US7392331B2 (en) 2004-08-31 2008-06-24 Micron Technology, Inc. System and method for transmitting data packets in a computer system having a memory hub architecture
US7681196B2 (en) * 2004-11-18 2010-03-16 Oracle International Corporation Providing optimal number of threads to applications performing multi-tasking using threads
US20060112240A1 (en) * 2004-11-24 2006-05-25 Walker Robert M Priority scheme for executing commands in memories
WO2006117746A1 (en) * 2005-05-04 2006-11-09 Nxp B.V. Memory controller and method for controlling access to a memory, as well as system comprising a memory controller
KR100784385B1 (ko) * 2005-08-10 2007-12-11 삼성전자주식회사 공유 자원에 대한 접근 요청을 중재하는 시스템 및 방법
JP5040660B2 (ja) * 2005-12-16 2012-10-03 日本電気株式会社 記憶領域割当システム及び方法と制御装置
US8868397B2 (en) * 2006-11-20 2014-10-21 Sonics, Inc. Transaction co-validation across abstraction layers
US7814243B2 (en) * 2007-06-01 2010-10-12 Sonics, Inc. Shared storage for multi-threaded ordered queues in an interconnect
US9588810B2 (en) * 2007-08-08 2017-03-07 Microsoft Technology Licensing, Llc Parallelism-aware memory request scheduling in shared memory controllers
US8260990B2 (en) * 2007-11-19 2012-09-04 Qualcomm Incorporated Selective preclusion of a bus access request
US8180975B2 (en) * 2008-02-26 2012-05-15 Microsoft Corporation Controlling interference in shared memory systems using parallelism-aware batch scheduling
US8799912B2 (en) * 2009-07-22 2014-08-05 Empire Technology Development Llc Application selection of memory request scheduling
US8607234B2 (en) 2009-07-22 2013-12-10 Empire Technology Development, Llc Batch scheduling with thread segregation and per thread type marking caps
US8839255B2 (en) * 2009-07-23 2014-09-16 Empire Technology Development Llc Scheduling of threads by batch scheduling
US8972995B2 (en) 2010-08-06 2015-03-03 Sonics, Inc. Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads
US8438306B2 (en) 2010-11-02 2013-05-07 Sonics, Inc. Apparatus and methods for on layer concurrency in an integrated circuit
KR101292309B1 (ko) * 2011-12-27 2013-07-31 숭실대학교산학협력단 반도체칩 및 메모리 제어방법, 그리고 그 방법을 컴퓨터에서 실행시키기 위한 프로그램을 기록한 기록매체
US9563369B2 (en) * 2014-04-14 2017-02-07 Microsoft Technology Licensing, Llc Fine-grained bandwidth provisioning in a memory controller
KR20170136382A (ko) * 2016-06-01 2017-12-11 주식회사 맴레이 메모리 컨트롤러, 그리고 이를 포함하는 메모리 모듈 및 프로세서
US10572399B2 (en) 2016-07-13 2020-02-25 Qualcomm Incorporated Memory request arbitration
US10481944B2 (en) * 2017-08-09 2019-11-19 Xilinx, Inc. Adaptive quality of service control circuit

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Also Published As

Publication number Publication date
EP1435039A4 (de) 2006-06-28
EP1435039B1 (de) 2007-11-07
EP1435039A1 (de) 2004-07-07
JP2005508550A (ja) 2005-03-31
ATE377793T1 (de) 2007-11-15
US6961834B2 (en) 2005-11-01
JP4095032B2 (ja) 2008-06-04
WO2003040927A1 (en) 2003-05-15
DE60223394T2 (de) 2008-08-28
US20030074519A1 (en) 2003-04-17

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