ATE377793T1 - Verfaren und vorrichtung zum einteilen von anforderungen für einen dynamischen direktzugriffsspeicherbaustein - Google Patents

Verfaren und vorrichtung zum einteilen von anforderungen für einen dynamischen direktzugriffsspeicherbaustein

Info

Publication number
ATE377793T1
ATE377793T1 AT02713653T AT02713653T ATE377793T1 AT E377793 T1 ATE377793 T1 AT E377793T1 AT 02713653 T AT02713653 T AT 02713653T AT 02713653 T AT02713653 T AT 02713653T AT E377793 T1 ATE377793 T1 AT E377793T1
Authority
AT
Austria
Prior art keywords
memory device
random access
access memory
dynamic random
assessing
Prior art date
Application number
AT02713653T
Other languages
English (en)
Inventor
Wolf-Dietrich Weber
Original Assignee
Sonics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=25525212&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=ATE377793(T1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Sonics Inc filed Critical Sonics Inc
Application granted granted Critical
Publication of ATE377793T1 publication Critical patent/ATE377793T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
AT02713653T 2001-10-12 2002-02-21 Verfaren und vorrichtung zum einteilen von anforderungen für einen dynamischen direktzugriffsspeicherbaustein ATE377793T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/977,510 US6961834B2 (en) 2001-10-12 2001-10-12 Method and apparatus for scheduling of requests to dynamic random access memory device

Publications (1)

Publication Number Publication Date
ATE377793T1 true ATE377793T1 (de) 2007-11-15

Family

ID=25525212

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02713653T ATE377793T1 (de) 2001-10-12 2002-02-21 Verfaren und vorrichtung zum einteilen von anforderungen für einen dynamischen direktzugriffsspeicherbaustein

Country Status (6)

Country Link
US (1) US6961834B2 (de)
EP (1) EP1435039B1 (de)
JP (1) JP4095032B2 (de)
AT (1) ATE377793T1 (de)
DE (1) DE60223394T2 (de)
WO (1) WO2003040927A1 (de)

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US7356633B2 (en) * 2002-05-03 2008-04-08 Sonics, Inc. Composing on-chip interconnects with configurable interfaces
US7194566B2 (en) * 2002-05-03 2007-03-20 Sonics, Inc. Communication system and method with configurable posting points
US7254603B2 (en) * 2002-05-03 2007-08-07 Sonics, Inc. On-chip inter-network performance optimization using configurable performance parameters
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US7836252B2 (en) * 2002-08-29 2010-11-16 Micron Technology, Inc. System and method for optimizing interconnections of memory devices in a multichip module
US7603441B2 (en) * 2002-12-27 2009-10-13 Sonics, Inc. Method and apparatus for automatic configuration of multiple on-chip interconnects
US7827283B2 (en) * 2003-02-19 2010-11-02 International Business Machines Corporation System for managing and controlling storage access requirements
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US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US9087036B1 (en) 2004-08-12 2015-07-21 Sonics, Inc. Methods and apparatuses for time annotated transaction level modeling
US7665069B2 (en) * 2003-10-31 2010-02-16 Sonics, Inc. Method and apparatus for establishing a quality of service model
US8504992B2 (en) * 2003-10-31 2013-08-06 Sonics, Inc. Method and apparatus for establishing a quality of service model
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US7120723B2 (en) 2004-03-25 2006-10-10 Micron Technology, Inc. System and method for memory hub-based expansion bus
US7590797B2 (en) * 2004-04-08 2009-09-15 Micron Technology, Inc. System and method for optimizing interconnections of components in a multichip memory module
US7392331B2 (en) 2004-08-31 2008-06-24 Micron Technology, Inc. System and method for transmitting data packets in a computer system having a memory hub architecture
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KR100784385B1 (ko) * 2005-08-10 2007-12-11 삼성전자주식회사 공유 자원에 대한 접근 요청을 중재하는 시스템 및 방법
US8225064B2 (en) * 2005-12-16 2012-07-17 Nec Corporation Storage region allocation system, storage region allocation method, and control apparatus
US8868397B2 (en) * 2006-11-20 2014-10-21 Sonics, Inc. Transaction co-validation across abstraction layers
US7814243B2 (en) * 2007-06-01 2010-10-12 Sonics, Inc. Shared storage for multi-threaded ordered queues in an interconnect
US9588810B2 (en) * 2007-08-08 2017-03-07 Microsoft Technology Licensing, Llc Parallelism-aware memory request scheduling in shared memory controllers
US8260990B2 (en) * 2007-11-19 2012-09-04 Qualcomm Incorporated Selective preclusion of a bus access request
US8180975B2 (en) * 2008-02-26 2012-05-15 Microsoft Corporation Controlling interference in shared memory systems using parallelism-aware batch scheduling
US8607234B2 (en) 2009-07-22 2013-12-10 Empire Technology Development, Llc Batch scheduling with thread segregation and per thread type marking caps
US8799912B2 (en) * 2009-07-22 2014-08-05 Empire Technology Development Llc Application selection of memory request scheduling
US8839255B2 (en) * 2009-07-23 2014-09-16 Empire Technology Development Llc Scheduling of threads by batch scheduling
US8972995B2 (en) 2010-08-06 2015-03-03 Sonics, Inc. Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads
US8438306B2 (en) 2010-11-02 2013-05-07 Sonics, Inc. Apparatus and methods for on layer concurrency in an integrated circuit
KR101292309B1 (ko) * 2011-12-27 2013-07-31 숭실대학교산학협력단 반도체칩 및 메모리 제어방법, 그리고 그 방법을 컴퓨터에서 실행시키기 위한 프로그램을 기록한 기록매체
US9563369B2 (en) * 2014-04-14 2017-02-07 Microsoft Technology Licensing, Llc Fine-grained bandwidth provisioning in a memory controller
KR20170136382A (ko) * 2016-06-01 2017-12-11 주식회사 맴레이 메모리 컨트롤러, 그리고 이를 포함하는 메모리 모듈 및 프로세서
US10572399B2 (en) * 2016-07-13 2020-02-25 Qualcomm Incorporated Memory request arbitration
US10481944B2 (en) * 2017-08-09 2019-11-19 Xilinx, Inc. Adaptive quality of service control circuit

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Also Published As

Publication number Publication date
JP4095032B2 (ja) 2008-06-04
EP1435039B1 (de) 2007-11-07
EP1435039A1 (de) 2004-07-07
DE60223394T2 (de) 2008-08-28
WO2003040927A1 (en) 2003-05-15
DE60223394D1 (de) 2007-12-20
EP1435039A4 (de) 2006-06-28
JP2005508550A (ja) 2005-03-31
US6961834B2 (en) 2005-11-01
US20030074519A1 (en) 2003-04-17

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