DE60223180D1 - Verfahren und prozessor zur parallelen verarbeitung einer logikereignis-simulation - Google Patents

Verfahren und prozessor zur parallelen verarbeitung einer logikereignis-simulation

Info

Publication number
DE60223180D1
DE60223180D1 DE60223180T DE60223180T DE60223180D1 DE 60223180 D1 DE60223180 D1 DE 60223180D1 DE 60223180 T DE60223180 T DE 60223180T DE 60223180 T DE60223180 T DE 60223180T DE 60223180 D1 DE60223180 D1 DE 60223180D1
Authority
DE
Germany
Prior art keywords
processor
associative memory
segments
memory mechanism
segment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60223180T
Other languages
English (en)
Inventor
Damian Dalton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Neosera Systems Ltd
Original Assignee
Neosera Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Neosera Systems Ltd filed Critical Neosera Systems Ltd
Application granted granted Critical
Publication of DE60223180D1 publication Critical patent/DE60223180D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
DE60223180T 2002-02-22 2002-02-22 Verfahren und prozessor zur parallelen verarbeitung einer logikereignis-simulation Expired - Lifetime DE60223180D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IE2002/000023 WO2003079237A1 (en) 2002-02-22 2002-02-22 A method and a processor for parallel processing of logic event simulation

Publications (1)

Publication Number Publication Date
DE60223180D1 true DE60223180D1 (de) 2007-12-06

Family

ID=27840067

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60223180T Expired - Lifetime DE60223180D1 (de) 2002-02-22 2002-02-22 Verfahren und prozessor zur parallelen verarbeitung einer logikereignis-simulation

Country Status (6)

Country Link
US (1) US20050228629A1 (de)
EP (1) EP1476828B1 (de)
AT (1) ATE376691T1 (de)
AU (1) AU2002233604A1 (de)
DE (1) DE60223180D1 (de)
WO (1) WO2003079237A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7114026B1 (en) * 2002-06-17 2006-09-26 Sandeep Khanna CAM device having multiple index generators
US20080092092A1 (en) * 2004-10-04 2008-04-17 Damian Jude Dalton Method and Processor for Power Analysis in Digital Circuits
WO2011080945A1 (ja) * 2009-12-28 2011-07-07 三菱電機株式会社 プログラム作成支援装置
US8738350B2 (en) * 2010-03-04 2014-05-27 Synopsys, Inc. Mixed concurrent and serial logic simulation of hardware designs
CN114841103B (zh) * 2022-07-01 2022-09-27 南昌大学 门级电路的并行仿真方法、系统、存储介质及设备
CN117112452B (zh) * 2023-08-24 2024-04-02 上海合芯数字科技有限公司 寄存器模拟配置方法、装置、计算机设备和存储介质

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0816470A (ja) * 1994-07-04 1996-01-19 Hitachi Ltd 並列計算機
KR20020077032A (ko) * 1999-06-28 2002-10-11 네오세라 시스템즈 리미티드 로직 이벤트 시뮬레이션
US20070219771A1 (en) * 2005-12-01 2007-09-20 Verheyen Henry T Branching and Behavioral Partitioning for a VLIW Processor

Also Published As

Publication number Publication date
US20050228629A1 (en) 2005-10-13
AU2002233604A1 (en) 2003-09-29
WO2003079237A1 (en) 2003-09-25
ATE376691T1 (de) 2007-11-15
EP1476828A1 (de) 2004-11-17
EP1476828B1 (de) 2007-10-24

Similar Documents

Publication Publication Date Title
ATE514982T1 (de) Verfahren und vorrichtungen zur auswertung regulärer ausdrücke beliebiger grösse
ATE434228T1 (de) Verfahren und vorrichtung für widerstand gegen hardware-hacking durch interne registerschnittstelle
DE60232227D1 (de) Schaltung und verfahren zur prüfung und reparatur
US20190378572A1 (en) Array organization and architecture to perform range-match operations with content addressable memory (cam) circuits
ATE376691T1 (de) Verfahren und prozessor zur parallelen verarbeitung einer logikereignis-simulation
Kornijcuk et al. Reconfigurable Spike Routing Architectures for On‐Chip Local Learning in Neuromorphic Systems
Fan et al. A gate-level method for transistor-level bridging fault diagnosis
US20030135838A1 (en) Method and apparatus for isolating the root of indeterminate logic values in an HDL simulation
Chaudhary et al. Low-power high-performance NAND match line content addressable memories
DE60024088D1 (de) Ereignis-simulation einer schaltkreislogik
Chou et al. Finding reset nondeterminism in RTL designs-scalable X-analysis methodology and case study
KR930015431A (ko) 중재자
US6877142B2 (en) Timing verifier for MOS devices and related method
Saab Parallel-concurrent fault simulation
US6654937B1 (en) Register file timing using static timing tools
US6438732B1 (en) Method and apparatus for modeling gate capacitance of symmetrically and asymmetrically sized differential cascode voltage swing logic (DCVSL)
Thatcher et al. Automatic partitioning and dynamic mixed-mode simulation
Dunlap et al. A Novel Circuit Authentication Scheme Based on Partial Polymorphic Gates
CN115292102A (zh) 仿真方法、电子设备、可读存储介质
EP0986015B1 (de) Verfahren zur Dynamischen Elektrischen Simulation von VLSI Schaltungen
Palit et al. Test Pattern Generation for Crosstalk Faults in DSM Chips using Modified PODEM
Bhavani DESIGN AND TESTABILITY OF Z-TERNARY CONTENT ADDRESSABLE MEMORY LOGIC
JPH10186001A (ja) 電子回路の消費電力計算方法および装置
Chang et al. Handling nondeterminism in logic simulation so that your waveform can be trusted again
SUNANDHA et al. Design of 128-Bit Comparator High Speed 4-Bit Architecture

Legal Events

Date Code Title Description
8332 No legal effect for de