ATE376691T1 - Verfahren und prozessor zur parallelen verarbeitung einer logikereignis-simulation - Google Patents

Verfahren und prozessor zur parallelen verarbeitung einer logikereignis-simulation

Info

Publication number
ATE376691T1
ATE376691T1 AT02700539T AT02700539T ATE376691T1 AT E376691 T1 ATE376691 T1 AT E376691T1 AT 02700539 T AT02700539 T AT 02700539T AT 02700539 T AT02700539 T AT 02700539T AT E376691 T1 ATE376691 T1 AT E376691T1
Authority
AT
Austria
Prior art keywords
processor
associative memory
segments
memory mechanism
segment
Prior art date
Application number
AT02700539T
Other languages
English (en)
Inventor
Damian Dalton
Original Assignee
Neosera Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Neosera Systems Ltd filed Critical Neosera Systems Ltd
Application granted granted Critical
Publication of ATE376691T1 publication Critical patent/ATE376691T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
AT02700539T 2002-02-22 2002-02-22 Verfahren und prozessor zur parallelen verarbeitung einer logikereignis-simulation ATE376691T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IE2002/000023 WO2003079237A1 (en) 2002-02-22 2002-02-22 A method and a processor for parallel processing of logic event simulation

Publications (1)

Publication Number Publication Date
ATE376691T1 true ATE376691T1 (de) 2007-11-15

Family

ID=27840067

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02700539T ATE376691T1 (de) 2002-02-22 2002-02-22 Verfahren und prozessor zur parallelen verarbeitung einer logikereignis-simulation

Country Status (6)

Country Link
US (1) US20050228629A1 (de)
EP (1) EP1476828B1 (de)
AT (1) ATE376691T1 (de)
AU (1) AU2002233604A1 (de)
DE (1) DE60223180D1 (de)
WO (1) WO2003079237A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7114026B1 (en) * 2002-06-17 2006-09-26 Sandeep Khanna CAM device having multiple index generators
WO2006038207A1 (en) * 2004-10-04 2006-04-13 University College Dublin A method and processor for power analysis in digital circuits
WO2011080945A1 (ja) * 2009-12-28 2011-07-07 三菱電機株式会社 プログラム作成支援装置
US8738350B2 (en) * 2010-03-04 2014-05-27 Synopsys, Inc. Mixed concurrent and serial logic simulation of hardware designs
CN114841103B (zh) * 2022-07-01 2022-09-27 南昌大学 门级电路的并行仿真方法、系统、存储介质及设备
CN117112452B (zh) * 2023-08-24 2024-04-02 上海合芯数字科技有限公司 寄存器模拟配置方法、装置、计算机设备和存储介质

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0816470A (ja) * 1994-07-04 1996-01-19 Hitachi Ltd 並列計算機
JP2003503800A (ja) * 1999-06-28 2003-01-28 ネオセラ・システムズ・リミテッド ロジック・イベント・シミュレーション
US20070219771A1 (en) * 2005-12-01 2007-09-20 Verheyen Henry T Branching and Behavioral Partitioning for a VLIW Processor

Also Published As

Publication number Publication date
US20050228629A1 (en) 2005-10-13
EP1476828A1 (de) 2004-11-17
DE60223180D1 (de) 2007-12-06
AU2002233604A1 (en) 2003-09-29
WO2003079237A1 (en) 2003-09-25
EP1476828B1 (de) 2007-10-24

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Legal Events

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