DE602009000943D1 - Verzögerungsunempfindlicher asynchroner Schaltkreis mit Verzögerungseinschaltschaltkreis - Google Patents

Verzögerungsunempfindlicher asynchroner Schaltkreis mit Verzögerungseinschaltschaltkreis

Info

Publication number
DE602009000943D1
DE602009000943D1 DE602009000943T DE602009000943T DE602009000943D1 DE 602009000943 D1 DE602009000943 D1 DE 602009000943D1 DE 602009000943 T DE602009000943 T DE 602009000943T DE 602009000943 T DE602009000943 T DE 602009000943T DE 602009000943 D1 DE602009000943 D1 DE 602009000943D1
Authority
DE
Germany
Prior art keywords
circuit
delay
output
input
turn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602009000943T
Other languages
English (en)
Inventor
Marc Renaudin
Ghislain Bouesse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TIEMPO
Original Assignee
TIEMPO
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TIEMPO filed Critical TIEMPO
Publication of DE602009000943D1 publication Critical patent/DE602009000943D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00346Modifications for eliminating interference or parasitic voltages or currents
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00323Delay compensation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019Variable delay
    • H03K2005/00058Variable delay controlled by a digital setting
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078Fixed delay
    • H03K2005/00084Fixed delay by trimming or adjusting the delay

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Electronic Switches (AREA)
DE602009000943T 2008-06-06 2009-05-26 Verzögerungsunempfindlicher asynchroner Schaltkreis mit Verzögerungseinschaltschaltkreis Active DE602009000943D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0803165A FR2932336B1 (fr) 2008-06-06 2008-06-06 Circuit asynchrone insensible aux delais avec circuit d'insertion de delai

Publications (1)

Publication Number Publication Date
DE602009000943D1 true DE602009000943D1 (de) 2011-05-05

Family

ID=40291252

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602009000943T Active DE602009000943D1 (de) 2008-06-06 2009-05-26 Verzögerungsunempfindlicher asynchroner Schaltkreis mit Verzögerungseinschaltschaltkreis

Country Status (5)

Country Link
US (1) US8171330B2 (de)
EP (1) EP2131495B1 (de)
AT (1) ATE503301T1 (de)
DE (1) DE602009000943D1 (de)
FR (1) FR2932336B1 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9213835B2 (en) * 2010-04-07 2015-12-15 Xilinx, Inc. Method and integrated circuit for secure encryption and decryption
US8522052B1 (en) 2010-04-07 2013-08-27 Xilinx, Inc. Method and integrated circuit for secure encryption and decryption
JP5761819B2 (ja) * 2010-06-17 2015-08-12 国立大学法人 奈良先端科学技術大学院大学 スキャン非同期記憶素子およびそれを備えた半導体集積回路ならびにその設計方法およびテストパターン生成方法
GB2487901B (en) * 2011-02-03 2019-12-04 Advanced Risc Mach Ltd Power signature obfuscation
US8958550B2 (en) * 2011-09-13 2015-02-17 Combined Conditional Access Development & Support. LLC (CCAD) Encryption operation with real data rounds, dummy data rounds, and delay periods
FR2980657B1 (fr) * 2011-09-28 2014-06-20 Oberthur Technologies Circuit electronique presentant une desynchronisation materielle au sein d'une periode d'horloge
US8854075B2 (en) * 2012-03-06 2014-10-07 Tiempo Delay-insensitive asynchronous circuit
US10043230B2 (en) * 2013-09-20 2018-08-07 Nvidia Corporation Approach to reducing voltage noise in a stalled data pipeline
FR3051084B1 (fr) * 2016-05-04 2019-08-02 Stmicroelectronics (Rousset) Sas Generateur de nombres d'oscillations
FR3051085B1 (fr) 2016-05-04 2020-02-14 Stmicroelectronics (Rousset) Sas Structure de multiplexeur
FR3051086B1 (fr) 2016-05-04 2019-07-26 Stmicroelectronics (Rousset) Sas Circuit de comptage d'impulsions
CN105871536B (zh) * 2016-06-14 2019-01-29 东南大学 一种基于随机延时的面向aes算法的抗功耗攻击方法
FR3054344B1 (fr) * 2016-07-25 2018-09-07 Tiempo Circuit integre protege.
CN108233914A (zh) * 2016-12-22 2018-06-29 电信科学技术研究院 一种随机噪声电流扰动电路
FR3065556B1 (fr) 2017-04-19 2020-11-06 Tiempo Circuit electronique securise par perturbation de son alimentation.
US11151287B2 (en) * 2018-12-07 2021-10-19 Stmicroelectronics Sa System and method for managing requests in an asynchronous pipeline
CN109495105A (zh) * 2018-12-29 2019-03-19 灿芯半导体(上海)有限公司 一种基于onfi的dll单元电路
FR3107150B1 (fr) * 2020-02-11 2022-01-21 Pyxalis Distribution et calibration de signaux synchronisés à travers un circuit intégré obtenu par photo-répétition
CN113839663B (zh) * 2021-09-26 2023-09-15 重庆大学 延迟不敏感异步电路单元、M×N-Join及其工作方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4330750A (en) * 1979-03-13 1982-05-18 International Computers Limited Variable delay circuits
US4637018A (en) * 1984-08-29 1987-01-13 Burroughs Corporation Automatic signal delay adjustment method
US5553276A (en) * 1993-06-30 1996-09-03 International Business Machines Corporation Self-time processor with dynamic clock generator having plurality of tracking elements for outputting sequencing signals to functional units
US6360288B1 (en) * 1997-10-17 2002-03-19 Sun Microsystems, Inc. Method and modules for control of pipelines carrying data using pipelines carrying control signals
EP2280502B1 (de) 1998-06-03 2018-05-02 Cryptography Research, Inc. Verwenden von unvorhersehbaren Informationen zu widerstehen die Entdeckung von Geheimnissen durch externe Überwachung
US6229364B1 (en) * 1999-03-23 2001-05-08 Infineon Technologies North America Corp. Frequency range trimming for a delay line
GB2365153A (en) * 2000-01-28 2002-02-13 Simon William Moore Microprocessor resistant to power analysis with an alarm state
US6927605B2 (en) * 2003-11-07 2005-08-09 Hewlett-Packard Development Company, L.P. System and method for dynamically varying a clock signal
EP1864380A2 (de) 2005-03-22 2007-12-12 Koninklijke Philips Electronics N.V. Elektronische schaltung mit einer asynchronen verzögerung
US7554374B2 (en) * 2007-03-30 2009-06-30 Sun Microsystems, Inc. Bounding a duty cycle using a C-element

Also Published As

Publication number Publication date
EP2131495B1 (de) 2011-03-23
EP2131495A1 (de) 2009-12-09
US8171330B2 (en) 2012-05-01
US20090307516A1 (en) 2009-12-10
ATE503301T1 (de) 2011-04-15
FR2932336A1 (fr) 2009-12-11
FR2932336B1 (fr) 2010-06-18

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