DE602008003969D1 - Überprüfungsverfahren - Google Patents
ÜberprüfungsverfahrenInfo
- Publication number
- DE602008003969D1 DE602008003969D1 DE602008003969T DE602008003969T DE602008003969D1 DE 602008003969 D1 DE602008003969 D1 DE 602008003969D1 DE 602008003969 T DE602008003969 T DE 602008003969T DE 602008003969 T DE602008003969 T DE 602008003969T DE 602008003969 D1 DE602008003969 D1 DE 602008003969D1
- Authority
- DE
- Germany
- Prior art keywords
- review process
- review
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP08002479A EP2088521B1 (de) | 2008-02-11 | 2008-02-11 | Überprüfungsverfahren |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE602008003969D1 true DE602008003969D1 (de) | 2011-01-27 |
Family
ID=39639005
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE602008003969T Active DE602008003969D1 (de) | 2008-02-11 | 2008-02-11 | Überprüfungsverfahren |
Country Status (2)
| Country | Link |
|---|---|
| EP (1) | EP2088521B1 (de) |
| DE (1) | DE602008003969D1 (de) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2508233A (en) * | 2012-11-27 | 2014-05-28 | Ibm | Verifying logic design of a processor with an instruction pipeline by comparing the output from first and second instances of the design |
| US9471327B2 (en) | 2013-08-20 | 2016-10-18 | International Business Machines Corporation | Verifying forwarding paths in pipelines |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE502005010558D1 (de) | 2005-09-15 | 2010-12-30 | Onespin Solutions Gmbh | Verfahren zur Bestimmung der Güte einer Menge von Eigenschaften, verwendbar zur Verifikation and zur Spezifikation von Schaltungen |
-
2008
- 2008-02-11 DE DE602008003969T patent/DE602008003969D1/de active Active
- 2008-02-11 EP EP08002479A patent/EP2088521B1/de active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP2088521A1 (de) | 2009-08-12 |
| EP2088521B1 (de) | 2010-12-15 |
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