DE602006017779D1 - Lithografische Masken und Verfahren - Google Patents

Lithografische Masken und Verfahren

Info

Publication number
DE602006017779D1
DE602006017779D1 DE602006017779T DE602006017779T DE602006017779D1 DE 602006017779 D1 DE602006017779 D1 DE 602006017779D1 DE 602006017779 T DE602006017779 T DE 602006017779T DE 602006017779 T DE602006017779 T DE 602006017779T DE 602006017779 D1 DE602006017779 D1 DE 602006017779D1
Authority
DE
Germany
Prior art keywords
methods
lithographic masks
lithographic
masks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006017779T
Other languages
English (en)
Inventor
Paul Uwe Schroeder
Klaus Herold
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE602006017779D1 publication Critical patent/DE602006017779D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441—Optical proximity correction [OPC]
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
DE602006017779T 2005-08-08 2006-07-24 Lithografische Masken und Verfahren Active DE602006017779D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/199,012 US7846616B2 (en) 2005-08-08 2005-08-08 Lithography masks and methods

Publications (1)

Publication Number Publication Date
DE602006017779D1 true DE602006017779D1 (de) 2010-12-09

Family

ID=36922238

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006017779T Active DE602006017779D1 (de) 2005-08-08 2006-07-24 Lithografische Masken und Verfahren

Country Status (3)

Country Link
US (1) US7846616B2 (de)
EP (1) EP1752825B1 (de)
DE (1) DE602006017779D1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100934855B1 (ko) * 2008-03-11 2010-01-06 주식회사 하이닉스반도체 노광마스크 및 이를 이용한 반도체소자 형성방법
KR101073293B1 (ko) * 2009-06-25 2011-10-12 삼성모바일디스플레이주식회사 하프톤 마스크와 그 제조방법 및 하프톤 마스크를 이용한 막 형성 방법
US8399157B2 (en) 2010-12-23 2013-03-19 Intel Corporation Lithography mask having sub-resolution phased assist features
WO2013101103A1 (en) * 2011-12-29 2013-07-04 Intel Corporation Lithography mask having sub-resolution phased assist features
US9046761B2 (en) 2010-12-23 2015-06-02 Intel Corporation Lithography mask having sub-resolution phased assist features
US8739078B2 (en) 2012-01-18 2014-05-27 International Business Machines Corporation Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections for semiconductor applications
US9436081B2 (en) * 2014-03-12 2016-09-06 Globalfoundries Inc. Methods of modifying masking reticles to remove forbidden pitch regions thereof
KR102305092B1 (ko) 2014-07-16 2021-09-24 삼성전자주식회사 포토리소그래피용 마스크와 그 제조 방법
CN108776421B (zh) * 2018-06-25 2021-08-10 上海华力集成电路制造有限公司 测试掩模版制造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5256505A (en) * 1992-08-21 1993-10-26 Microunity Systems Engineering Lithographical mask for controlling the dimensions of resist patterns
US6433878B1 (en) * 2001-01-29 2002-08-13 Timbre Technology, Inc. Method and apparatus for the determination of mask rules using scatterometry
US6519760B2 (en) 2001-02-28 2003-02-11 Asml Masktools, B.V. Method and apparatus for minimizing optical proximity effects
US6792591B2 (en) 2001-02-28 2004-09-14 Asml Masktools B.V. Method of identifying an extreme interaction pitch region, methods of designing mask patterns and manufacturing masks, device manufacturing methods and computer programs
DE10230532B4 (de) 2002-07-05 2007-03-08 Infineon Technologies Ag Verfahren zum Bestimmen des Aufbaus einer Maske zum Mikrostrukturieren von Halbleitersubstraten mittels Fotolithographie
US6711732B1 (en) * 2002-07-26 2004-03-23 Taiwan Semiconductor Manufacturing Company Full sized scattering bar alt-PSM technique for IC manufacturing in sub-resolution era
US7251377B2 (en) 2003-04-29 2007-07-31 Synopsys, Inc. Cell library that can automatically avoid forbidden pitches
US6973636B2 (en) * 2003-10-17 2005-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method of defining forbidden pitches for a lithography exposure tool
SG111289A1 (en) * 2003-11-05 2005-05-30 Asml Masktools Bv A method for performing transmission tuning of a mask pattern to improve process latitude
US6977715B2 (en) * 2004-05-19 2005-12-20 Nanya Technology Corp. Method for optimizing NILS of exposed lines
US7632610B2 (en) * 2004-09-02 2009-12-15 Intel Corporation Sub-resolution assist features
US7129181B2 (en) * 2004-09-17 2006-10-31 Palo Alto Research Center Incorporated Sub-resolution gaps generated by controlled over-etching
US7332812B2 (en) * 2005-04-14 2008-02-19 Infineon Technologies Ag Memory card with connecting portions for connection to an adapter

Also Published As

Publication number Publication date
EP1752825B1 (de) 2010-10-27
US20070031737A1 (en) 2007-02-08
US7846616B2 (en) 2010-12-07
EP1752825A2 (de) 2007-02-14
EP1752825A3 (de) 2009-07-22

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