DE602006006964D1 - Verzögerungsregelschleife mit asynchronem Entscheidungselement - Google Patents

Verzögerungsregelschleife mit asynchronem Entscheidungselement

Info

Publication number
DE602006006964D1
DE602006006964D1 DE602006006964T DE602006006964T DE602006006964D1 DE 602006006964 D1 DE602006006964 D1 DE 602006006964D1 DE 602006006964 T DE602006006964 T DE 602006006964T DE 602006006964 T DE602006006964 T DE 602006006964T DE 602006006964 D1 DE602006006964 D1 DE 602006006964D1
Authority
DE
Germany
Prior art keywords
control loop
delay control
decision element
asynchronous decision
asynchronous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006006964T
Other languages
English (en)
Inventor
Michael Lewis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of DE602006006964D1 publication Critical patent/DE602006006964D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
DE602006006964T 2006-02-09 2006-02-09 Verzögerungsregelschleife mit asynchronem Entscheidungselement Active DE602006006964D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP06002663A EP1819050B1 (de) 2006-02-09 2006-02-09 Verzögerungsregelschleife mit asynchronem Entscheidungselement

Publications (1)

Publication Number Publication Date
DE602006006964D1 true DE602006006964D1 (de) 2009-07-09

Family

ID=35945314

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006006964T Active DE602006006964D1 (de) 2006-02-09 2006-02-09 Verzögerungsregelschleife mit asynchronem Entscheidungselement

Country Status (5)

Country Link
US (1) US8008907B2 (de)
EP (1) EP1819050B1 (de)
KR (1) KR100745855B1 (de)
CN (1) CN100578934C (de)
DE (1) DE602006006964D1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BRPI0516496A (pt) * 2004-10-15 2008-09-09 Trico Products Corp Of Tenness sistema de detecção de objeto com autocalibração
US20080272817A1 (en) * 2007-05-04 2008-11-06 Niels Fricke Integrated Circuit on a Semiconductor Chip with a Phase Shift Circuit and a Method for Digital Phase Shifting
DE102009028350A1 (de) * 2009-08-07 2011-02-10 Pmd Technologies Gmbh Verfahren und Schaltung zur Erzeugung mehrerer phasenstarr gekoppelter Modulationssignale in unterschiedlichen relativen Phasenlagen
US8542049B1 (en) * 2012-04-18 2013-09-24 Texas Instruments Incorporated Methods and delay circuits for generating a plurality of delays in delay lines
FR3051929B1 (fr) * 2016-05-31 2018-06-22 Gorgy Timing Circuit d'arbitrage temporel
US9825636B1 (en) * 2016-10-20 2017-11-21 Arm Limited Apparatus and method for reduced latency signal synchronization
TWI670939B (zh) * 2018-12-03 2019-09-01 新唐科技股份有限公司 具有校正功能的延遲線電路及其校正方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL288519A (de) * 1962-04-25
US5034967A (en) * 1988-11-14 1991-07-23 Datapoint Corporation Metastable-free digital synchronizer with low phase error
JP2966422B2 (ja) * 1988-11-28 1999-10-25 株式会社アドバンテスト タイミング較正装置
US5822768A (en) * 1996-01-11 1998-10-13 Opti Inc. Dual ported memory for a unified memory architecture
KR980008121A (ko) * 1996-07-04 1998-04-30 김태신 전자동 차광장치
US6043694A (en) * 1998-06-24 2000-03-28 Siemens Aktiengesellschaft Lock arrangement for a calibrated DLL in DDR SDRAM applications
US6390579B1 (en) * 1999-04-15 2002-05-21 Hewlett-Packard Company Pulse width modulator using delay-line technology with automatic calibration of delays to desired operating frequency
US6661860B1 (en) * 2000-01-04 2003-12-09 Massachusetts Institute Of Technology Multiple arbiter jitter estimation system and related techniques
JP3968963B2 (ja) * 2000-06-30 2007-08-29 コニカミノルタホールディングス株式会社 ディジタルｐｌｌパルス発生装置
US7571359B2 (en) * 2000-07-31 2009-08-04 Massachusetts Institute Of Technology Clock distribution circuits and methods of operating same that use multiple clock circuits connected by phase detector circuits to generate and synchronize local clock signals
US6779123B2 (en) * 2001-02-28 2004-08-17 Intel Corporation Calibrating return time for resynchronizing data demodulated from a master slave bus
US7067763B2 (en) * 2002-05-17 2006-06-27 Gsi Group Corporation High speed, laser-based marking method and system for producing machine readable marks on workpieces and semiconductor devices with reduced subsurface damage produced thereby
US7403053B2 (en) * 2002-12-19 2008-07-22 Intel Corporation Power supply dependent delay compensation
KR100546368B1 (ko) * 2003-08-22 2006-01-26 삼성전자주식회사 센터링 에러를 일으키는 클럭 스큐를 자체적으로 보상하는메모리 장치 및 그 클럭 스큐 보상 방법
JP4284527B2 (ja) * 2004-03-26 2009-06-24 日本電気株式会社 メモリインターフェイス制御回路

Also Published As

Publication number Publication date
EP1819050B1 (de) 2009-05-27
US8008907B2 (en) 2011-08-30
EP1819050A1 (de) 2007-08-15
KR100745855B1 (ko) 2007-08-02
US20070182423A1 (en) 2007-08-09
CN100578934C (zh) 2010-01-06
CN101018050A (zh) 2007-08-15

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Legal Events

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8364 No opposition during term of opposition