DE602004029664D1 - Datenverarbeitung wobei gleichzeitig ausgeführte prozesse durch einen fifo-puffer kommunizieren - Google Patents

Datenverarbeitung wobei gleichzeitig ausgeführte prozesse durch einen fifo-puffer kommunizieren

Info

Publication number
DE602004029664D1
DE602004029664D1 DE602004029664T DE602004029664T DE602004029664D1 DE 602004029664 D1 DE602004029664 D1 DE 602004029664D1 DE 602004029664 T DE602004029664 T DE 602004029664T DE 602004029664 T DE602004029664 T DE 602004029664T DE 602004029664 D1 DE602004029664 D1 DE 602004029664D1
Authority
DE
Germany
Prior art keywords
data
grain
stream
buffer
wrap around
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004029664T
Other languages
English (en)
Inventor
Om Prakash Gangwal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Trident Microsystems Far East Ltd Cayman Islands
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602004029664D1 publication Critical patent/DE602004029664D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Memory System (AREA)
DE602004029664T 2003-04-16 2004-04-08 Datenverarbeitung wobei gleichzeitig ausgeführte prozesse durch einen fifo-puffer kommunizieren Expired - Lifetime DE602004029664D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP03101030 2003-04-16
PCT/IB2004/050412 WO2004092945A2 (en) 2003-04-16 2004-04-08 Data processing in which concurrently executed processes communicate via a fifo buffer

Publications (1)

Publication Number Publication Date
DE602004029664D1 true DE602004029664D1 (de) 2010-12-02

Family

ID=33185932

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004029664T Expired - Lifetime DE602004029664D1 (de) 2003-04-16 2004-04-08 Datenverarbeitung wobei gleichzeitig ausgeführte prozesse durch einen fifo-puffer kommunizieren

Country Status (8)

Country Link
US (1) US7594046B2 (de)
EP (1) EP1618466B1 (de)
JP (1) JP2006523884A (de)
KR (1) KR101032563B1 (de)
CN (1) CN100430886C (de)
AT (1) ATE485557T1 (de)
DE (1) DE602004029664D1 (de)
WO (1) WO2004092945A2 (de)

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US8046506B2 (en) * 2006-03-21 2011-10-25 Mediatek Inc. FIFO system and operating method thereof
US7571357B2 (en) * 2006-08-22 2009-08-04 International Business Machines Corporation Memory wrap test mode using functional read/write buffers
US10592444B2 (en) 2013-01-07 2020-03-17 Wave Computing, Inc. Reconfigurable interconnected programmable processors
US9588773B2 (en) 2013-01-07 2017-03-07 Wave Computing, Inc. Software based application specific integrated circuit
US10218357B2 (en) 2013-11-02 2019-02-26 Wave Computing, Inc. Logical elements with switchable connections for multifunction operation
US10203935B2 (en) 2013-11-02 2019-02-12 Wave Computing, Inc. Power control within a dataflow processor
WO2015066561A1 (en) * 2013-11-02 2015-05-07 Wave Semiconductor, Inc. Logical elements with switchable connections
US20150324136A1 (en) * 2014-05-07 2015-11-12 Lsi Corporation Storage system having fifo storage and reserved storage
US9449131B2 (en) * 2014-06-02 2016-09-20 Xilinx, Inc. Extracting system architecture in high level synthesis
US10073773B2 (en) 2015-02-21 2018-09-11 Wave Computing, Inc. Instruction paging in reconfigurable fabric
US10437728B2 (en) 2015-02-21 2019-10-08 Wave Computing, Inc. Branchless instruction paging in reconfigurable fabric
US10505704B1 (en) 2015-08-02 2019-12-10 Wave Computing, Inc. Data uploading to asynchronous circuitry using circular buffer control
US10659396B2 (en) 2015-08-02 2020-05-19 Wave Computing, Inc. Joining data within a reconfigurable fabric
US10564929B2 (en) 2016-09-01 2020-02-18 Wave Computing, Inc. Communication between dataflow processing units and memories
US10719470B2 (en) 2016-09-26 2020-07-21 Wave Computing, Inc. Reconfigurable fabric direct memory access with multiple read or write elements
US11106976B2 (en) 2017-08-19 2021-08-31 Wave Computing, Inc. Neural network output layer for machine learning
US10949328B2 (en) 2017-08-19 2021-03-16 Wave Computing, Inc. Data flow graph computation using exceptions
CN109839477A (zh) * 2017-11-24 2019-06-04 内蒙古光能科技有限公司 一种crds气体浓度检测仪加速量测的方法
US10528131B2 (en) * 2018-05-16 2020-01-07 Tobii Ab Method to reliably detect correlations between gaze and stimuli
US11645178B2 (en) 2018-07-27 2023-05-09 MIPS Tech, LLC Fail-safe semi-autonomous or autonomous vehicle processor array redundancy which permits an agent to perform a function based on comparing valid output from sets of redundant processors
US11481472B2 (en) 2019-04-01 2022-10-25 Wave Computing, Inc. Integer matrix multiplication engine using pipelining
US10997102B2 (en) 2019-04-01 2021-05-04 Wave Computing, Inc. Multidimensional address generation for direct memory access
US11227030B2 (en) 2019-04-01 2022-01-18 Wave Computing, Inc. Matrix multiplication engine using pipelining
US11934308B2 (en) 2019-04-01 2024-03-19 Wave Computing, Inc. Processor cluster address generation

Family Cites Families (9)

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Publication number Priority date Publication date Assignee Title
US4623997A (en) * 1984-12-13 1986-11-18 United Technologies Corporation Coherent interface with wraparound receive and transmit memories
JP2703417B2 (ja) * 1991-04-05 1998-01-26 富士通株式会社 受信バッファ
US5379240A (en) * 1993-03-08 1995-01-03 Cyrix Corporation Shifter/rotator with preconditioned data
US5502833A (en) * 1994-03-30 1996-03-26 International Business Machines Corporation System and method for management of a predictive split cache for supporting FIFO queues
US5608889A (en) * 1994-08-17 1997-03-04 Ceridian Corporation DNA controller with wrap-around buffer mode
JP2550921B2 (ja) * 1994-08-26 1996-11-06 日本電気株式会社 環状バッファ制御装置
DE19511774A1 (de) * 1995-03-30 1996-10-02 Siemens Ag Speicheranordnung mit einem als Ringspeicher betreibbaren Speicher
US6622198B2 (en) * 2000-08-31 2003-09-16 United Memories, Inc. Look-ahead, wrap-around first-in, first-out integrated (FIFO) circuit device architecture
US7633549B2 (en) * 2004-05-03 2009-12-15 Ati Technologies, Inc. Apparatus and method for image rendering

Also Published As

Publication number Publication date
EP1618466A2 (de) 2006-01-25
CN1774694A (zh) 2006-05-17
JP2006523884A (ja) 2006-10-19
ATE485557T1 (de) 2010-11-15
KR101032563B1 (ko) 2011-05-06
WO2004092945A3 (en) 2005-01-20
WO2004092945A2 (en) 2004-10-28
CN100430886C (zh) 2008-11-05
US20070133399A1 (en) 2007-06-14
KR20060004674A (ko) 2006-01-12
US7594046B2 (en) 2009-09-22
EP1618466B1 (de) 2010-10-20

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: TRIDENT MICROSYSTEMS (FAR EAST) LTD., GRAND CA, KY