DE602004024024D1 - Mikroprozessor mit einem Stapelcachespeicher mit variabler Latenz - Google Patents
Mikroprozessor mit einem Stapelcachespeicher mit variabler LatenzInfo
- Publication number
- DE602004024024D1 DE602004024024D1 DE602004024024T DE602004024024T DE602004024024D1 DE 602004024024 D1 DE602004024024 D1 DE 602004024024D1 DE 602004024024 T DE602004024024 T DE 602004024024T DE 602004024024 T DE602004024024 T DE 602004024024T DE 602004024024 D1 DE602004024024 D1 DE 602004024024D1
- Authority
- DE
- Germany
- Prior art keywords
- microprocessor
- stack cache
- variable latency
- latency stack
- variable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30134—Register stacks; shift registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/759,483 US7191291B2 (en) | 2003-01-16 | 2004-01-16 | Microprocessor with variable latency stack cache |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602004024024D1 true DE602004024024D1 (de) | 2009-12-24 |
Family
ID=34620718
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602004024024T Active DE602004024024D1 (de) | 2004-01-16 | 2004-08-05 | Mikroprozessor mit einem Stapelcachespeicher mit variabler Latenz |
Country Status (5)
Country | Link |
---|---|
US (1) | US7191291B2 (de) |
EP (2) | EP2101267B1 (de) |
CN (1) | CN1632877B (de) |
DE (1) | DE602004024024D1 (de) |
TW (1) | TWI294590B (de) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100377115C (zh) * | 2005-11-11 | 2008-03-26 | 中国科学院计算技术研究所 | 适用于上下文切换的栈高速缓冲存储器及缓冲存储方法 |
US7870542B1 (en) * | 2006-04-05 | 2011-01-11 | Mcafee, Inc. | Calling system, method and computer program product |
US8533778B1 (en) * | 2006-06-23 | 2013-09-10 | Mcafee, Inc. | System, method and computer program product for detecting unwanted effects utilizing a virtual machine |
US7937533B2 (en) * | 2007-12-10 | 2011-05-03 | International Business Machines Corporation | Structure for handling data requests |
US8032713B2 (en) * | 2007-12-10 | 2011-10-04 | International Business Machines Corporation | Structure for handling data access |
US7949830B2 (en) * | 2007-12-10 | 2011-05-24 | International Business Machines Corporation | System and method for handling data requests |
US9053031B2 (en) * | 2007-12-10 | 2015-06-09 | International Business Machines Corporation | System and method for handling data access |
WO2012103253A2 (en) | 2011-01-27 | 2012-08-02 | Soft Machines, Inc. | Multilevel conversion table cache for translating guest instructions to native instructions |
WO2012103373A2 (en) | 2011-01-27 | 2012-08-02 | Soft Machines, Inc. | Variable caching structure for managing physical storage |
WO2012103359A2 (en) | 2011-01-27 | 2012-08-02 | Soft Machines, Inc. | Hardware acceleration components for translating guest instructions to native instructions |
EP2668565B1 (de) | 2011-01-27 | 2019-11-06 | Intel Corporation | Gastinstruktion für ein mapping auf basis nativer instruktionen mithilfe eines look-aside-umwandlungspuffers auf einem prozessor |
WO2012103367A2 (en) | 2011-01-27 | 2012-08-02 | Soft Machines, Inc. | Guest to native block address mappings and management of native code storage |
WO2012103245A2 (en) | 2011-01-27 | 2012-08-02 | Soft Machines Inc. | Guest instruction block with near branching and far branching sequence construction to native instruction block |
US20130222422A1 (en) * | 2012-02-29 | 2013-08-29 | Mediatek Inc. | Data buffering apparatus capable of alternately transmitting stored partial data of input images merged in one merged image to image/video processing device and related data buffering method |
US9348385B2 (en) | 2012-07-09 | 2016-05-24 | L. Pierre deRochement | Hybrid computing module |
EP2972798B1 (de) | 2013-03-15 | 2020-06-17 | Intel Corporation | Verfahren und vorrichtung für eine gastadressenstapelemulation mit unterstützung einer spekulation |
WO2014151652A1 (en) | 2013-03-15 | 2014-09-25 | Soft Machines Inc | Method and apparatus to allow early dependency resolution and data forwarding in a microprocessor |
CN104699627B (zh) * | 2013-12-06 | 2019-05-07 | 上海芯豪微电子有限公司 | 一种缓存系统和方法 |
GB2525314B (en) * | 2014-01-17 | 2016-02-24 | Imagination Tech Ltd | Stack pointer value prediction |
US9646154B2 (en) * | 2014-12-12 | 2017-05-09 | Microsoft Technology Licensing, Llc | Return oriented programming (ROP) attack protection |
JP6207765B2 (ja) | 2014-12-14 | 2017-10-04 | ヴィア アライアンス セミコンダクター カンパニー リミテッド | モードに応じてセットの1つ又は複数を選択的に選択するように動的に構成可能であるマルチモード・セット・アソシエイティブ・キャッシュ・メモリ |
US10719434B2 (en) | 2014-12-14 | 2020-07-21 | Via Alliance Semiconductors Co., Ltd. | Multi-mode set associative cache memory dynamically configurable to selectively allocate into all or a subset of its ways depending on the mode |
WO2016097808A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Dynamic cache replacement way selection based on address tag bits |
GB2542831B (en) * | 2015-09-30 | 2018-05-30 | Imagination Tech Ltd | Fetch unit for predicting target for subroutine return instructions |
US10275356B2 (en) * | 2015-12-11 | 2019-04-30 | Quanta Computer Inc. | Component carrier with converter board |
US20230101038A1 (en) * | 2021-09-29 | 2023-03-30 | Advanced Micro Devices, Inc. | Deterministic mixed latency cache |
CN114333930B (zh) * | 2021-12-23 | 2024-03-08 | 合肥兆芯电子有限公司 | 多通道存储器存储装置、控制电路单元及其数据读取方法 |
GB2622286A (en) * | 2022-09-02 | 2024-03-13 | Advanced Risc Mach Ltd | Synchronization of load/store operations |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3401376A (en) * | 1965-11-26 | 1968-09-10 | Burroughs Corp | Central processor |
US3810117A (en) * | 1972-10-20 | 1974-05-07 | Ibm | Stack mechanism for a data processor |
US5043870A (en) | 1982-02-24 | 1991-08-27 | At&T Bell Laboratories | Computer with automatic mapping of memory contents into machine registers during program execution |
GB2260429B (en) | 1991-10-11 | 1995-05-24 | Intel Corp | Versatile cache memory |
US5500950A (en) | 1993-01-29 | 1996-03-19 | Motorola, Inc. | Data processor with speculative data transfer and address-free retry |
US6151661A (en) | 1994-03-03 | 2000-11-21 | International Business Machines Corporation | Cache memory storage space management system and method |
US5751990A (en) | 1994-04-26 | 1998-05-12 | International Business Machines Corporation | Abridged virtual address cache directory |
KR970029072A (ko) | 1995-11-17 | 1997-06-26 | 김주용 | 이중 디렉토리 가상 캐쉬 및 그 제어 방법 |
JP3634379B2 (ja) | 1996-01-24 | 2005-03-30 | サン・マイクロシステムズ・インコーポレイテッド | スタックキャッシングのための方法及び装置 |
US6038643A (en) * | 1996-01-24 | 2000-03-14 | Sun Microsystems, Inc. | Stack management unit and method for a processor having a stack |
US5930820A (en) * | 1996-03-18 | 1999-07-27 | Advanced Micro Devices, Inc. | Data cache and method using a stack memory for storing stack data separate from cache line storage |
US5835968A (en) | 1996-04-17 | 1998-11-10 | Advanced Micro Devices, Inc. | Apparatus for providing memory and register operands concurrently to functional units |
US5953741A (en) | 1996-11-27 | 1999-09-14 | Vlsi Technology, Inc. | Stack cache for stack-based processor and method thereof |
US5956752A (en) * | 1996-12-16 | 1999-09-21 | Intel Corporation | Method and apparatus for accessing a cache using index prediction |
US6009499A (en) | 1997-03-31 | 1999-12-28 | Sun Microsystems, Inc | Pipelined stack caching circuit |
JPH11212788A (ja) | 1998-01-28 | 1999-08-06 | Toshiba Corp | プロセッサのデータ供給装置 |
US6275903B1 (en) | 1998-04-22 | 2001-08-14 | Sun Microsystems, Inc. | Stack cache miss handling |
US6496902B1 (en) | 1998-12-31 | 2002-12-17 | Cray Inc. | Vector and scalar data cache for a vector multiprocessor |
US6425055B1 (en) * | 1999-02-24 | 2002-07-23 | Intel Corporation | Way-predicting cache memory |
US6622211B2 (en) | 2001-08-15 | 2003-09-16 | Ip-First, L.L.C. | Virtual set cache that redirects store data to correct virtual set to avoid virtual set store miss penalty |
TW556212B (en) | 2002-01-14 | 2003-10-01 | Ip First Llc | L2 cache LRU generation method and apparatus |
US6671196B2 (en) * | 2002-02-28 | 2003-12-30 | Sun Microsystems, Inc. | Register stack in cache memory |
US7467377B2 (en) | 2002-10-22 | 2008-12-16 | Intel Corporation | Methods and apparatus for compiler managed first cache bypassing |
US7203798B2 (en) | 2003-03-20 | 2007-04-10 | Matsushita Electric Industrial Co., Ltd. | Data memory cache unit and data memory cache system |
-
2004
- 2004-01-16 US US10/759,483 patent/US7191291B2/en active Active
- 2004-08-05 EP EP09159693.2A patent/EP2101267B1/de active Active
- 2004-08-05 DE DE602004024024T patent/DE602004024024D1/de active Active
- 2004-08-05 EP EP04254724A patent/EP1555617B1/de active Active
- 2004-08-06 TW TW093123711A patent/TWI294590B/zh active
-
2005
- 2005-01-10 CN CN200510003692.6A patent/CN1632877B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
EP1555617A2 (de) | 2005-07-20 |
CN1632877A (zh) | 2005-06-29 |
TW200525431A (en) | 2005-08-01 |
EP1555617A3 (de) | 2006-06-07 |
US7191291B2 (en) | 2007-03-13 |
CN1632877B (zh) | 2011-01-12 |
EP1555617B1 (de) | 2009-11-11 |
TWI294590B (en) | 2008-03-11 |
EP2101267A3 (de) | 2009-11-04 |
US20040162947A1 (en) | 2004-08-19 |
EP2101267A2 (de) | 2009-09-16 |
EP2101267B1 (de) | 2013-10-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |