DE602004019114D1 - Programmierbarer logikbaustein mit programmierbaren multi-gigabit-sendern/-empfängern - Google Patents

Programmierbarer logikbaustein mit programmierbaren multi-gigabit-sendern/-empfängern

Info

Publication number
DE602004019114D1
DE602004019114D1 DE602004019114T DE602004019114T DE602004019114D1 DE 602004019114 D1 DE602004019114 D1 DE 602004019114D1 DE 602004019114 T DE602004019114 T DE 602004019114T DE 602004019114 T DE602004019114 T DE 602004019114T DE 602004019114 D1 DE602004019114 D1 DE 602004019114D1
Authority
DE
Germany
Prior art keywords
programmable
gigabit
transmitters
receivers
logic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004019114T
Other languages
English (en)
Inventor
Eric D Groen
Charles W Boecker
William C Black
Scott A Irwin
Joseph N Kryzak
Yiqin Chen
Andrews G Jenkins
Aaron J Hoelscher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of DE602004019114D1 publication Critical patent/DE602004019114D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
DE602004019114T 2003-09-11 2004-09-10 Programmierbarer logikbaustein mit programmierbaren multi-gigabit-sendern/-empfängern Active DE602004019114D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/661,016 US7406118B2 (en) 2003-09-11 2003-09-11 Programmable logic device including programmable multi-gigabit transceivers
PCT/US2004/029864 WO2005027344A2 (en) 2003-09-11 2004-09-10 Programmable logic device including programmable multi-gigabit transceivers

Publications (1)

Publication Number Publication Date
DE602004019114D1 true DE602004019114D1 (de) 2009-03-05

Family

ID=34273780

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004019114T Active DE602004019114D1 (de) 2003-09-11 2004-09-10 Programmierbarer logikbaustein mit programmierbaren multi-gigabit-sendern/-empfängern

Country Status (6)

Country Link
US (1) US7406118B2 (de)
EP (1) EP1665072B1 (de)
JP (1) JP4750704B2 (de)
CA (1) CA2536624C (de)
DE (1) DE602004019114D1 (de)
WO (1) WO2005027344A2 (de)

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US7471752B2 (en) * 2004-08-06 2008-12-30 Lattice Semiconductor Corporation Data transmission synchronization
US7958294B1 (en) * 2004-11-19 2011-06-07 Xilinx, Inc. Integrated circuit having data transceivers and method of positioning circuits on an integrated circuit
US7558552B1 (en) * 2004-11-19 2009-07-07 Xilinx, Inc. Integrated circuit and method of generating a bias current for a plurality of data transceivers
US20070013411A1 (en) * 2005-07-14 2007-01-18 Kazi Asaduzzaman Apparatus and methods for programmable slew rate control in transmitter circuits
US7729415B1 (en) * 2006-02-14 2010-06-01 Xilinx, Inc. High-speed interface for a programmable device
WO2008070138A2 (en) 2006-12-05 2008-06-12 Rambus Inc. Methods and circuits for asymmetric distribution of channel equalization between transceiver devices
US7688106B1 (en) * 2007-02-27 2010-03-30 Altera Corporation High-speed serial interface circuitry for programmable logic device integrated circuits
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US8261002B2 (en) * 2007-09-11 2012-09-04 Quicklogic Corporation PHY-less ULPI and UTMI bridges
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US9531646B1 (en) 2009-12-07 2016-12-27 Altera Corporation Multi-protocol configurable transceiver including configurable deskew in an integrated circuit
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US8732375B1 (en) * 2010-04-01 2014-05-20 Altera Corporation Multi-protocol configurable transceiver with independent channel-based PCS in an integrated circuit
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US8760188B2 (en) * 2011-06-30 2014-06-24 Silicon Image, Inc. Configurable multi-dimensional driver and receiver
US9170952B1 (en) * 2011-12-28 2015-10-27 Altera Corporation Configurable multi-standard device interface
US9148341B2 (en) * 2012-03-26 2015-09-29 Jds Uniphase Corporation Upgrading a programmable logic gate array in an in-service pluggable transceiver
US9036755B2 (en) * 2012-09-28 2015-05-19 Liming Xiu Circuits and methods for time-average frequency based clock data recovery
US9811618B1 (en) * 2013-03-07 2017-11-07 Xilinx, Inc. Simulation of system designs
US11075854B2 (en) 2017-10-17 2021-07-27 Arista Networks, Inc. System for reducing latency in network devices
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CN115694740B (zh) * 2022-12-30 2023-03-10 井芯微电子技术(天津)有限公司 Uvm验证平台系统和验证方法

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Also Published As

Publication number Publication date
WO2005027344A2 (en) 2005-03-24
US7406118B2 (en) 2008-07-29
CA2536624C (en) 2009-06-02
EP1665072B1 (de) 2009-01-14
JP2007505578A (ja) 2007-03-08
EP1665072A2 (de) 2006-06-07
CA2536624A1 (en) 2005-03-24
JP4750704B2 (ja) 2011-08-17
WO2005027344A3 (en) 2005-07-28
US20050058187A1 (en) 2005-03-17

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