DE602004011889D1 - Anordnung und Verfahren zur Durchführung einer frühen Korrektur von falschen Vorhersagen beim bedingten Verzweigungsbefehl - Google Patents

Anordnung und Verfahren zur Durchführung einer frühen Korrektur von falschen Vorhersagen beim bedingten Verzweigungsbefehl

Info

Publication number
DE602004011889D1
DE602004011889D1 DE602004011889T DE602004011889T DE602004011889D1 DE 602004011889 D1 DE602004011889 D1 DE 602004011889D1 DE 602004011889 T DE602004011889 T DE 602004011889T DE 602004011889 T DE602004011889 T DE 602004011889T DE 602004011889 D1 DE602004011889 D1 DE 602004011889D1
Authority
DE
Germany
Prior art keywords
arrangement
branch instruction
conditional branch
early correction
false predictions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004011889T
Other languages
English (en)
Other versions
DE602004011889T2 (de
Inventor
Gerard M Col
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Via Technologies Inc
Original Assignee
Via Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Technologies Inc filed Critical Via Technologies Inc
Publication of DE602004011889D1 publication Critical patent/DE602004011889D1/de
Application granted granted Critical
Publication of DE602004011889T2 publication Critical patent/DE602004011889T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3848—Speculative instruction execution using hybrid branch prediction, e.g. selection between prediction techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
DE602004011889T 2004-02-04 2004-09-14 Anordnung und Verfahren zur Durchführung einer frühen Korrektur von falschen Vorhersagen beim bedingten Verzweigungsbefehl Expired - Lifetime DE602004011889T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US771682 2004-02-04
US10/771,682 US7107438B2 (en) 2003-02-04 2004-02-04 Pipelined microprocessor, apparatus, and method for performing early correction of conditional branch instruction mispredictions

Publications (2)

Publication Number Publication Date
DE602004011889D1 true DE602004011889D1 (de) 2008-04-03
DE602004011889T2 DE602004011889T2 (de) 2009-02-26

Family

ID=34679365

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004011889T Expired - Lifetime DE602004011889T2 (de) 2004-02-04 2004-09-14 Anordnung und Verfahren zur Durchführung einer frühen Korrektur von falschen Vorhersagen beim bedingten Verzweigungsbefehl

Country Status (5)

Country Link
US (1) US7107438B2 (de)
EP (1) EP1562107B1 (de)
CN (1) CN100377078C (de)
DE (1) DE602004011889T2 (de)
TW (1) TWI288351B (de)

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US7617387B2 (en) * 2006-09-27 2009-11-10 Qualcomm Incorporated Methods and system for resolving simultaneous predicted branch instructions
US7984279B2 (en) * 2006-11-03 2011-07-19 Qualcomm Incorporated System and method for using a working global history register
US20080222392A1 (en) * 2007-03-09 2008-09-11 On Demand Microelectronics Method and arrangements for pipeline processing of instructions
US7711935B2 (en) * 2007-04-30 2010-05-04 Netlogic Microsystems, Inc. Universal branch identifier for invalidation of speculative instructions
US7802078B2 (en) * 2008-09-09 2010-09-21 Via Technologies, Inc. REP MOVE string instruction execution by selecting loop microinstruction sequence or unrolled sequence based on flag state indicative of low count repeat
US7979675B2 (en) * 2009-02-12 2011-07-12 Via Technologies, Inc. Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution
US8145890B2 (en) * 2009-02-12 2012-03-27 Via Technologies, Inc. Pipelined microprocessor with fast conditional branch instructions based on static microcode-implemented instruction state
EP2624126B1 (de) * 2011-04-07 2016-11-02 VIA Technologies, Inc. Effiziente konditionale Arithmetik- und Logikeinheit- (ALU) -Anweisung in leseanschlussbegrenztem Registerdatei-Mikroprozessor
US9128701B2 (en) * 2011-04-07 2015-09-08 Via Technologies, Inc. Generating constant for microinstructions from modified immediate field during instruction translation
US20160170770A1 (en) * 2014-12-12 2016-06-16 Qualcomm Incorporated Providing early instruction execution in an out-of-order (ooo) processor, and related apparatuses, methods, and computer-readable media
US10545766B2 (en) 2017-04-18 2020-01-28 International Business Machines Corporation Register restoration using transactional memory register snapshots
US10963261B2 (en) 2017-04-18 2021-03-30 International Business Machines Corporation Sharing snapshots across save requests
US10838733B2 (en) 2017-04-18 2020-11-17 International Business Machines Corporation Register context restoration based on rename register recovery
US10782979B2 (en) 2017-04-18 2020-09-22 International Business Machines Corporation Restoring saved architected registers and suppressing verification of registers to be restored
US10572265B2 (en) 2017-04-18 2020-02-25 International Business Machines Corporation Selecting register restoration or register reloading
US11010192B2 (en) 2017-04-18 2021-05-18 International Business Machines Corporation Register restoration using recovery buffers
US10740108B2 (en) 2017-04-18 2020-08-11 International Business Machines Corporation Management of store queue based on restoration operation
GB2592661B (en) * 2020-03-05 2022-05-11 Advanced Risc Mach Ltd An apparatus and method for performing branch prediction
TWI785880B (zh) * 2021-07-06 2022-12-01 阿比特電子科技股份有限公司 錯誤偵測校正方法及其電路
CN117008977B (zh) * 2023-08-08 2024-03-19 上海合芯数字科技有限公司 一种可变执行周期的指令执行方法、系统和计算机设备

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US5093777A (en) 1989-06-12 1992-03-03 Bull Hn Information Systems Inc. Method and apparatus for predicting address of a subsequent cache request upon analyzing address patterns stored in separate miss stack
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US6079014A (en) * 1993-12-02 2000-06-20 Intel Corporation Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state
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US5701426A (en) * 1995-03-31 1997-12-23 Bull Information Systems Inc. Data processing system and method using cache miss address prediction and forced LRU status in a cache memory to improve cache hit ratio
US5606682A (en) * 1995-04-07 1997-02-25 Motorola Inc. Data processor with branch target address cache and subroutine return address cache and method of operation
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Also Published As

Publication number Publication date
TWI288351B (en) 2007-10-11
US7107438B2 (en) 2006-09-12
EP1562107B1 (de) 2008-02-20
US20040158697A1 (en) 2004-08-12
EP1562107A1 (de) 2005-08-10
TW200527288A (en) 2005-08-16
CN1658154A (zh) 2005-08-24
DE602004011889T2 (de) 2009-02-26
CN100377078C (zh) 2008-03-26

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