DE602004011241D1 - Analog-frontend mit eingebauter entzerrung - Google Patents

Analog-frontend mit eingebauter entzerrung

Info

Publication number
DE602004011241D1
DE602004011241D1 DE602004011241T DE602004011241T DE602004011241D1 DE 602004011241 D1 DE602004011241 D1 DE 602004011241D1 DE 602004011241 T DE602004011241 T DE 602004011241T DE 602004011241 T DE602004011241 T DE 602004011241T DE 602004011241 D1 DE602004011241 D1 DE 602004011241D1
Authority
DE
Germany
Prior art keywords
decoration
built
analog frontend
frontend
analog
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004011241T
Other languages
English (en)
Other versions
DE602004011241T2 (de
Inventor
William C Black
Charles W Boecker
Eric D Groen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Publication of DE602004011241D1 publication Critical patent/DE602004011241D1/de
Application granted granted Critical
Publication of DE602004011241T2 publication Critical patent/DE602004011241T2/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03878—Line equalisers; line build-out devices
    • H04L25/03885—Line equalisers; line build-out devices adaptive

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Dc Digital Transmission (AREA)
  • Amplifiers (AREA)
DE602004011241T 2003-09-11 2004-09-10 Analog-frontend mit eingebauter entzerrung Active DE602004011241T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US659803 2003-09-11
US10/659,803 US7480347B2 (en) 2003-09-11 2003-09-11 Analog front-end having built-in equalization and applications thereof
PCT/US2004/029763 WO2005027443A1 (en) 2003-09-11 2004-09-10 Analog front-end with built-in equalization

Publications (2)

Publication Number Publication Date
DE602004011241D1 true DE602004011241D1 (de) 2008-02-21
DE602004011241T2 DE602004011241T2 (de) 2008-12-24

Family

ID=34273529

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004011241T Active DE602004011241T2 (de) 2003-09-11 2004-09-10 Analog-frontend mit eingebauter entzerrung

Country Status (6)

Country Link
US (2) US7480347B2 (de)
EP (1) EP1665690B1 (de)
JP (1) JP4850706B2 (de)
CA (1) CA2536628C (de)
DE (1) DE602004011241T2 (de)
WO (1) WO2005027443A1 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7343535B2 (en) * 2002-02-06 2008-03-11 Avago Technologies General Ip Dte Ltd Embedded testing capability for integrated serializer/deserializers
US20050063431A1 (en) * 2003-09-19 2005-03-24 Gallup Kendra J. Integrated optics and electronics
US20050063648A1 (en) * 2003-09-19 2005-03-24 Wilson Robert Edward Alignment post for optical subassemblies made with cylindrical rods, tubes, spheres, or similar features
US7520679B2 (en) * 2003-09-19 2009-04-21 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Optical device package with turning mirror and alignment post
US6982437B2 (en) * 2003-09-19 2006-01-03 Agilent Technologies, Inc. Surface emitting laser package having integrated optical element and alignment post
US6953990B2 (en) * 2003-09-19 2005-10-11 Agilent Technologies, Inc. Wafer-level packaging of optoelectronic devices
US7352835B1 (en) 2003-09-22 2008-04-01 Altera Corporation Clock data recovery circuitry with dynamic support for changing data rates and a dynamically adjustable PPM detector
US20050213995A1 (en) * 2004-03-26 2005-09-29 Myunghee Lee Low power and low jitter optical receiver for fiber optic communication link
US8139628B1 (en) 2005-01-10 2012-03-20 Marvell International Ltd. Method and device to compensate for baseline wander
KR100732510B1 (ko) * 2005-12-02 2007-06-27 엘에스산전 주식회사 네트워크 시스템
US8031763B2 (en) * 2006-12-28 2011-10-04 Intel Corporation Automatic tuning circuit for a continuous-time equalizer
JP2010516104A (ja) * 2007-01-09 2010-05-13 ラムバス・インコーポレーテッド 等化送信機および動作方法
US7724815B1 (en) * 2007-02-27 2010-05-25 Xilinx, Inc. Method and apparatus for a programmably terminated receiver
US7724028B1 (en) * 2008-04-11 2010-05-25 Xilinx, Inc. Clocking for a hardwired core embedded in a host integrated circuit device
US8559582B2 (en) * 2010-09-13 2013-10-15 Altera Corporation Techniques for varying a periodic signal based on changes in a data rate
US8736306B2 (en) 2011-08-04 2014-05-27 Micron Technology, Inc. Apparatuses and methods of communicating differential serial signals including charge injection
JP5878340B2 (ja) * 2011-11-15 2016-03-08 ルネサスエレクトロニクス株式会社 半導体装置及びセンサシステム
CN103078650A (zh) * 2013-01-06 2013-05-01 中国电子科技集团公司第十研究所 高速数传接收机
US8958513B1 (en) * 2013-03-15 2015-02-17 Xilinx, Inc. Clock and data recovery with infinite pull-in range
US9484867B2 (en) 2014-07-18 2016-11-01 Qualcomm Incorporated Wideband low-power amplifier
US10038647B1 (en) 2016-05-13 2018-07-31 Xilinx, Inc. Circuit for and method of routing data between die of an integrated circuit
US9983889B1 (en) 2016-05-13 2018-05-29 Xilinx, Inc. Booting of integrated circuits
US10224884B2 (en) 2017-02-07 2019-03-05 Xilinx, Inc. Circuit for and method of implementing a multifunction output generator
US10348290B1 (en) 2017-03-28 2019-07-09 Xilinx, Inc. System and method for transmitter

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3437344B2 (ja) * 1995-08-23 2003-08-18 富士通株式会社 波形整形回路
JP3576702B2 (ja) * 1996-06-12 2004-10-13 富士通株式会社 可変ハイパスフィルタ
US6240131B1 (en) 1997-06-30 2001-05-29 Advanced Micro Devices, Inc. Digitally controlled transmission line equalizer
US6188721B1 (en) * 1998-04-17 2001-02-13 Lucent Technologies, Inc. System and method for adaptive equalization of a waveform independent of absolute waveform peak value
US6531931B1 (en) 1998-06-01 2003-03-11 Agere Systems Inc. Circuit and method for equalization of signals received over a communication system transmission line
US6424480B1 (en) * 1999-09-28 2002-07-23 Koninklijke Philips Electronics N.V. Magnetic medium storage apparatus with read channel having a programmable write-to-read suppression
US6492876B1 (en) 2001-10-25 2002-12-10 National Semiconductor Corporation Low power analog equalizer with variable op-amp gain
US6545622B1 (en) 2001-10-25 2003-04-08 National Semiconductor Corporation Low power analog equalizer with current mode digital to analog converter

Also Published As

Publication number Publication date
EP1665690B1 (de) 2008-01-09
US20050058222A1 (en) 2005-03-17
US20090116585A1 (en) 2009-05-07
JP4850706B2 (ja) 2012-01-11
CA2536628C (en) 2014-05-06
CA2536628A1 (en) 2005-03-24
DE602004011241T2 (de) 2008-12-24
US7480347B2 (en) 2009-01-20
JP2007505576A (ja) 2007-03-08
US7830985B2 (en) 2010-11-09
EP1665690A1 (de) 2006-06-07
WO2005027443A1 (en) 2005-03-24

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