DE60122402D1 - Vorrichtung und Verfahren zur Bestimmung der Phasendifferenz zwischen einem Abtasttakt und einem abgetasteten Signal - Google Patents

Vorrichtung und Verfahren zur Bestimmung der Phasendifferenz zwischen einem Abtasttakt und einem abgetasteten Signal

Info

Publication number
DE60122402D1
DE60122402D1 DE60122402T DE60122402T DE60122402D1 DE 60122402 D1 DE60122402 D1 DE 60122402D1 DE 60122402 T DE60122402 T DE 60122402T DE 60122402 T DE60122402 T DE 60122402T DE 60122402 D1 DE60122402 D1 DE 60122402D1
Authority
DE
Germany
Prior art keywords
determining
phase difference
sampling clock
sampled signal
sampled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60122402T
Other languages
English (en)
Inventor
Hakan Ozdemir
Jason D Byrne
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Application granted granted Critical
Publication of DE60122402D1 publication Critical patent/DE60122402D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G11B20/10037—A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
DE60122402T 2000-02-14 2001-01-30 Vorrichtung und Verfahren zur Bestimmung der Phasendifferenz zwischen einem Abtasttakt und einem abgetasteten Signal Expired - Lifetime DE60122402D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/503,453 US6775084B1 (en) 2000-02-14 2000-02-14 Circuit and method for determining the phase difference between a sample clock and a sampled signal

Publications (1)

Publication Number Publication Date
DE60122402D1 true DE60122402D1 (de) 2006-10-05

Family

ID=24002150

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60122402T Expired - Lifetime DE60122402D1 (de) 2000-02-14 2001-01-30 Vorrichtung und Verfahren zur Bestimmung der Phasendifferenz zwischen einem Abtasttakt und einem abgetasteten Signal

Country Status (4)

Country Link
US (1) US6775084B1 (de)
EP (1) EP1126616B1 (de)
JP (1) JP2001273720A (de)
DE (1) DE60122402D1 (de)

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US7830630B2 (en) * 2001-06-28 2010-11-09 Stmicroelectronics, Inc. Circuit and method for detecting the phase of a servo signal
US7839594B2 (en) * 2001-06-28 2010-11-23 Stmicroelectronics, Inc. Data-storage disk having few or no spin-up wedges and method for writing servo wedges onto the disk
US7082005B2 (en) * 2001-10-24 2006-07-25 Agere Systems Inc. Servo data detection in the presence or absence of radial incoherence using digital interpolators
US7190754B1 (en) * 2001-12-24 2007-03-13 Rambus Inc. Transceiver with selectable data rate
US20030123174A1 (en) * 2001-12-28 2003-07-03 Mark Hennecken Continuously variable storage device data transfer rate
US7793020B1 (en) 2002-11-27 2010-09-07 International Business Machines Corporation Apparatus and method to read information from an information storage medium
US7602863B2 (en) * 2004-09-24 2009-10-13 Seagate Technology Llc Method and apparatus for providing iterative timing recovery
US7773324B2 (en) * 2005-04-12 2010-08-10 Stmicroelectronics, Inc. Phase acquisition loop for a read channel and related read channel, system, and method
US7768732B2 (en) * 2005-04-12 2010-08-03 Stmicroelectronics, Inc. Gain controller for a gain loop of a read channel and related gain loops, read channels, systems, and methods
US7675702B2 (en) * 2006-05-24 2010-03-09 Seagate Technology Llc Reduced convolution for repetitive disturbance rejection
US7764759B2 (en) * 2006-06-13 2010-07-27 Gennum Corporation Linear sample and hold phase detector for clocking circuits
US7974035B2 (en) * 2006-06-29 2011-07-05 Broadcom Corporation Timing recovery optimization using disk clock
US7869547B1 (en) * 2007-02-15 2011-01-11 Link—A—Media Devices Corporation Preamble acquisition without second order timing loops
US8036312B2 (en) 2007-03-30 2011-10-11 Freescale Semiconductor, Inc. System and method for determining signal phase
US7995304B2 (en) * 2009-05-27 2011-08-09 Seagate Technology Llc Circuits that use a postamble signal to determine phase and frequency errors in the acquisition of a preamble signal
BR112012022931B1 (pt) 2010-03-26 2020-09-29 Shell Internationale Research Maatschappij B.V Método para identificar discrepâncias de temporizações de relógio em pelo menos um relógio de interesse que esteja associado com um receptor sísmico
US8049982B1 (en) 2010-07-30 2011-11-01 Lsi Corporation Methods and apparatus for measuring servo address mark distance in a read channel using selective fine phase estimate
US8780470B1 (en) 2013-03-11 2014-07-15 Western Digital Technologies, Inc. Disk drive adjusting digital phase locked loop over sector data with frequency induced phase error measured over preamble

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3956623A (en) * 1974-10-21 1976-05-11 Gte Automatic Electric Laboratories Incorporated Digital phase detector
US4412339A (en) 1981-09-24 1983-10-25 Advanced Micro Devices, Inc. Zero-crossing interpolator to reduce isochronous distortion in a digital FSK modem
IT1155558B (it) * 1982-07-19 1987-01-28 Cselt Centro Studi Lab Telecom Procedimento e strumento per la misura dell ampiezza di un segnale periodico fortemente affetto da rumore e senza riferimento di fase
JP2589759B2 (ja) 1988-05-27 1997-03-12 松下電器産業株式会社 データ識別装置
US5359631A (en) 1992-09-30 1994-10-25 Cirrus Logic, Inc. Timing recovery circuit for synchronous waveform sampling
US5486867A (en) 1993-11-30 1996-01-23 Raytheon Company High resolution digital phase detector
JP3077881B2 (ja) * 1995-03-07 2000-08-21 日本電気株式会社 復調方法及び復調装置
US5848099A (en) 1996-05-30 1998-12-08 Qualcomm Incorporation Method and system for testing phase imbalance in QPSK receivers
US5835295A (en) * 1996-11-18 1998-11-10 Cirrus Logice, Inc. Zero phase restart interpolated timing recovery in a sampled amplitude read channel
US6529460B1 (en) 1998-01-31 2003-03-04 Seagate Technology Llc Detection of pulse peak instance and amplitude in a storage drive
US6307696B1 (en) * 1999-05-06 2001-10-23 Maxtor Corporation Digital zero-phase restart circuit
US6493403B1 (en) * 2000-02-02 2002-12-10 Infineon Technologies North America Corp. Asynchronous timing for interpolated timing recovery

Also Published As

Publication number Publication date
EP1126616B1 (de) 2006-08-23
JP2001273720A (ja) 2001-10-05
EP1126616A3 (de) 2003-11-12
US6775084B1 (en) 2004-08-10
EP1126616A2 (de) 2001-08-22

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