DE60115609D1 - Datenverarbeitungsarchitektur mit bereichsprüfung für matrix - Google Patents

Datenverarbeitungsarchitektur mit bereichsprüfung für matrix

Info

Publication number
DE60115609D1
DE60115609D1 DE60115609T DE60115609T DE60115609D1 DE 60115609 D1 DE60115609 D1 DE 60115609D1 DE 60115609 T DE60115609 T DE 60115609T DE 60115609 T DE60115609 T DE 60115609T DE 60115609 D1 DE60115609 D1 DE 60115609D1
Authority
DE
Germany
Prior art keywords
matrix
data processing
processing architecture
field testing
testing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60115609T
Other languages
English (en)
Other versions
DE60115609T2 (de
Inventor
Ashley Saulsbury
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22690256&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE60115609(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE60115609D1 publication Critical patent/DE60115609D1/de
Publication of DE60115609T2 publication Critical patent/DE60115609T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/14—Layer or component removable to expose adhesive
    • Y10T428/149—Sectional layer removable

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
DE60115609T 2000-03-08 2001-03-08 Datenverarbeitungsarchitektur mit bereichsprüfung für matrix Expired - Fee Related DE60115609T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US18773900P 2000-03-08 2000-03-08
US187739P 2000-03-08
PCT/US2001/007384 WO2001067238A1 (en) 2000-03-08 2001-03-08 Processing architecture having an array bounds check capability

Publications (2)

Publication Number Publication Date
DE60115609D1 true DE60115609D1 (de) 2006-01-12
DE60115609T2 DE60115609T2 (de) 2006-08-17

Family

ID=22690256

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60115609T Expired - Fee Related DE60115609T2 (de) 2000-03-08 2001-03-08 Datenverarbeitungsarchitektur mit bereichsprüfung für matrix

Country Status (8)

Country Link
US (1) US6892295B2 (de)
EP (1) EP1261914B1 (de)
JP (1) JP2003526155A (de)
KR (1) KR20030016234A (de)
AU (1) AU2001245519A1 (de)
DE (1) DE60115609T2 (de)
HK (1) HK1048538B (de)
WO (1) WO2001067238A1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6408383B1 (en) * 2000-05-04 2002-06-18 Sun Microsystems, Inc. Array access boundary check by executing BNDCHK instruction with comparison specifiers
US20030023958A1 (en) * 2001-07-17 2003-01-30 Patel Mukesh K. Intermediate language accelerator chip
US7013321B2 (en) 2001-11-21 2006-03-14 Sun Microsystems, Inc. Methods and apparatus for performing parallel integer multiply accumulate operations
US7558816B2 (en) 2001-11-21 2009-07-07 Sun Microsystems, Inc. Methods and apparatus for performing pixel average operations
GB2393289C (en) * 2002-09-17 2008-02-28 Micron Europe Ltd Method for load balancing a line of parallel processing elements
US7574466B2 (en) 2003-04-23 2009-08-11 Micron Technology, Inc. Method for finding global extrema of a set of shorts distributed across an array of parallel processing elements
US7447720B2 (en) 2003-04-23 2008-11-04 Micron Technology, Inc. Method for finding global extrema of a set of bytes distributed across an array of parallel processing elements
US7454451B2 (en) 2003-04-23 2008-11-18 Micron Technology, Inc. Method for finding local extrema of a set of values for a parallel processing element
US7890735B2 (en) * 2004-08-30 2011-02-15 Texas Instruments Incorporated Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture
US7401202B1 (en) 2004-09-14 2008-07-15 Azul Systems, Inc. Memory addressing
US20060271542A1 (en) * 2005-05-25 2006-11-30 Harris Steven T Clustered object state using logical actions
US7577801B1 (en) 2005-12-06 2009-08-18 Azul Systems, Inc. Array access
US8464030B2 (en) * 2010-04-09 2013-06-11 International Business Machines Corporation Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits
WO2012134122A2 (en) * 2011-03-26 2012-10-04 Samsung Electronics Co., Ltd. Method and apparatus for eliminating partially redundant array bounds checks in an embedded compiler
WO2013089709A1 (en) * 2011-12-14 2013-06-20 Intel Corporation System, apparatus and method for generating a loop alignment count or a loop alignment mask
US10324728B2 (en) 2015-12-17 2019-06-18 International Business Machines Corporation Lightweight interrupts for condition checking
US9875104B2 (en) * 2016-02-03 2018-01-23 Google Llc Accessing data in multi-dimensional tensors

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4293907A (en) 1978-12-29 1981-10-06 Bell Telephone Laboratories, Incorporated Data processing apparatus having op-code extension register
US4542456A (en) 1982-04-28 1985-09-17 At&T Bell Laboratories Method and apparatus for performing range checks
EP0540155A3 (en) * 1991-10-29 1993-07-21 Advanced Micro Devices, Inc. Digital limit checking system
US5687338A (en) 1994-03-01 1997-11-11 Intel Corporation Method and apparatus for maintaining a macro instruction for refetching in a pipelined processor
WO1997027544A1 (en) 1996-01-24 1997-07-31 Sun Microsystems, Inc. Processor with accelerated array access bounds checking
US5900011A (en) 1996-07-01 1999-05-04 Sun Microsystems, Inc. Integrated processor/memory device with victim data cache
US5909572A (en) 1996-12-02 1999-06-01 Compaq Computer Corp. System and method for conditionally moving an operand from a source register to a destination register
US5933650A (en) 1997-10-09 1999-08-03 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US6085208A (en) * 1997-10-23 2000-07-04 Advanced Micro Devices, Inc. Leading one prediction unit for normalizing close path subtraction results within a floating point arithmetic unit
US6035390A (en) * 1998-01-12 2000-03-07 International Business Machines Corporation Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical operation

Also Published As

Publication number Publication date
WO2001067238A1 (en) 2001-09-13
JP2003526155A (ja) 2003-09-02
EP1261914B1 (de) 2005-12-07
HK1048538A1 (en) 2003-04-04
US20020029332A1 (en) 2002-03-07
AU2001245519A1 (en) 2001-09-17
EP1261914A1 (de) 2002-12-04
DE60115609T2 (de) 2006-08-17
HK1048538B (zh) 2006-08-04
KR20030016234A (ko) 2003-02-26
US6892295B2 (en) 2005-05-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee