DE60108908D1 - Frequenzteiler für gebrochenzahlige frequenzteilerverhältnisse - Google Patents

Frequenzteiler für gebrochenzahlige frequenzteilerverhältnisse

Info

Publication number
DE60108908D1
DE60108908D1 DE60108908T DE60108908T DE60108908D1 DE 60108908 D1 DE60108908 D1 DE 60108908D1 DE 60108908 T DE60108908 T DE 60108908T DE 60108908 T DE60108908 T DE 60108908T DE 60108908 D1 DE60108908 D1 DE 60108908D1
Authority
DE
Germany
Prior art keywords
frequency
phase
broken
ratio conditions
parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60108908T
Other languages
English (en)
Other versions
DE60108908T2 (de
Inventor
Zeijl Thomas Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Application granted granted Critical
Publication of DE60108908D1 publication Critical patent/DE60108908D1/de
Publication of DE60108908T2 publication Critical patent/DE60108908T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/68—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • General Induction Heating (AREA)
DE60108908T 2001-07-06 2001-07-06 Frequenzteiler für gebrochenzahlige frequenzteilerverhältnisse Expired - Lifetime DE60108908T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/NL2001/000514 WO2003005588A1 (en) 2001-07-06 2001-07-06 Fractional frequency divider

Publications (2)

Publication Number Publication Date
DE60108908D1 true DE60108908D1 (de) 2005-03-17
DE60108908T2 DE60108908T2 (de) 2006-02-16

Family

ID=19760755

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60108908T Expired - Lifetime DE60108908T2 (de) 2001-07-06 2001-07-06 Frequenzteiler für gebrochenzahlige frequenzteilerverhältnisse

Country Status (5)

Country Link
US (1) US7084678B2 (de)
EP (1) EP1405417B1 (de)
AT (1) ATE289132T1 (de)
DE (1) DE60108908T2 (de)
WO (1) WO2003005588A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100652809B1 (ko) * 2005-11-03 2006-12-04 삼성전자주식회사 가변 저항 및 가변 용량을 이용한 광대역 다상 필터
KR100758713B1 (ko) * 2006-10-18 2007-09-14 (주)에프씨아이 다중위상필터
DE102008005981B4 (de) 2008-01-24 2010-07-15 Atmel Automotive Gmbh Empfänger, Verfahren zum Empfang und Verwendung eines In-Phase-Signals und eines Quadraturphase-Signals
EP2345153B1 (de) * 2008-11-11 2012-09-19 Telefonaktiebolaget L M Ericsson (PUBL) Frequenzgenerator
JP5438440B2 (ja) * 2009-09-08 2014-03-12 株式会社豊田中央研究所 アクティブポリフェーズフィルタ
US8493107B2 (en) * 2010-07-27 2013-07-23 Mediatek Inc. Clock generator for generating output clock having non-harmonic relationship with input clock and related clock generating method thereof
US8816780B2 (en) 2010-07-27 2014-08-26 Mediatek Inc. Apparatus and method for calibrating timing mismatch of edge rotator operating on multiple phases of oscillator
EP2849356B1 (de) * 2013-09-12 2016-07-06 Alcatel Lucent Vorrichtung, Fahrzeug, Verfahren und Computerprogramm für einen mobilen Relais-Sender-Empfänger und ein Telematikmodul eines Fahrzeugs
US10924125B2 (en) 2018-10-23 2021-02-16 Taiwan Semiconductor Manufacturing Company Ltd. Frequency divider circuit, method and compensation circuit for frequency divider circuit

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5059924A (en) * 1988-11-07 1991-10-22 Level One Communications, Inc. Clock adapter using a phase locked loop configured as a frequency multiplier with a non-integer feedback divider
GB2228638A (en) * 1989-02-22 1990-08-29 Stc Plc Digital phase shifter
FR2697703B1 (fr) * 1992-10-30 1995-01-13 Sgs Thomson Microelectronics Multiplexeur recevant en entrée une pluralité de signaux identiques mais déphasés.
JPH1032486A (ja) * 1996-07-16 1998-02-03 Fujitsu Ltd 分数分周器及びｐｌｌ回路
US5889436A (en) * 1996-11-01 1999-03-30 National Semiconductor Corporation Phase locked loop fractional pulse swallowing frequency synthesizer
US5970110A (en) * 1998-01-09 1999-10-19 Neomagic Corp. Precise, low-jitter fractional divider using counter of rotating clock phases
US5977805A (en) * 1998-01-21 1999-11-02 Atmel Corporation Frequency synthesis circuit tuned by digital words
US6114914A (en) * 1999-05-19 2000-09-05 Cypress Semiconductor Corp. Fractional synthesis scheme for generating periodic signals
US6526374B1 (en) * 1999-12-13 2003-02-25 Agere Systems Inc. Fractional PLL employing a phase-selection feedback counter
FI108380B (fi) * 2000-03-10 2002-01-15 Nokia Corp Monimurtojakajainen esijakaja
US6822488B1 (en) * 2000-07-31 2004-11-23 Skyworks Solutions, Inc. Frequency synthesizer
US6788154B2 (en) * 2001-01-26 2004-09-07 True Circuits, Inc. Phase-locked loop with composite feedback signal formed from phase-shifted variants of output signal
EP1244214A1 (de) * 2001-03-23 2002-09-25 STMicroelectronics Limited Phasengesteuerter digitaler Frequenzteiler

Also Published As

Publication number Publication date
DE60108908T2 (de) 2006-02-16
ATE289132T1 (de) 2005-02-15
EP1405417B1 (de) 2005-02-09
US20040252805A1 (en) 2004-12-16
EP1405417A1 (de) 2004-04-07
US7084678B2 (en) 2006-08-01
WO2003005588A1 (en) 2003-01-16

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