DE60037255D1 - Verfahren zur Herstellung von Zwischenverbindungen in Halbleitervorrichtungen - Google Patents
Verfahren zur Herstellung von Zwischenverbindungen in HalbleitervorrichtungenInfo
- Publication number
- DE60037255D1 DE60037255D1 DE60037255T DE60037255T DE60037255D1 DE 60037255 D1 DE60037255 D1 DE 60037255D1 DE 60037255 T DE60037255 T DE 60037255T DE 60037255 T DE60037255 T DE 60037255T DE 60037255 D1 DE60037255 D1 DE 60037255D1
- Authority
- DE
- Germany
- Prior art keywords
- interconnects
- preparation
- semiconductor devices
- semiconductor
- devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00830810A EP1213758B1 (de) | 2000-12-11 | 2000-12-11 | Verfahren zur Herstellung von Zwischenverbindungen in Halbleitervorrichtungen |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60037255D1 true DE60037255D1 (de) | 2008-01-10 |
Family
ID=8175584
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60037255T Expired - Lifetime DE60037255D1 (de) | 2000-12-11 | 2000-12-11 | Verfahren zur Herstellung von Zwischenverbindungen in Halbleitervorrichtungen |
Country Status (3)
Country | Link |
---|---|
US (1) | US6475898B2 (de) |
EP (1) | EP1213758B1 (de) |
DE (1) | DE60037255D1 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6965165B2 (en) | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4624749A (en) * | 1985-09-03 | 1986-11-25 | Harris Corporation | Electrodeposition of submicrometer metallic interconnect for integrated circuits |
US5145571A (en) * | 1990-08-03 | 1992-09-08 | Bipolar Integrated Technology, Inc. | Gold interconnect with sidewall-spacers |
US5461003A (en) * | 1994-05-27 | 1995-10-24 | Texas Instruments Incorporated | Multilevel interconnect structure with air gaps formed between metal leads |
US5900668A (en) * | 1995-11-30 | 1999-05-04 | Advanced Micro Devices, Inc. | Low capacitance interconnection |
DE19716044C2 (de) * | 1997-04-17 | 1999-04-08 | Univ Dresden Tech | Verfahren zum selektiven galvanischen Aufbringen von Lotdepots auf Leiterplatten |
US6309956B1 (en) * | 1997-09-30 | 2001-10-30 | Intel Corporation | Fabricating low K dielectric interconnect systems by using dummy structures to enhance process |
US6100194A (en) * | 1998-06-22 | 2000-08-08 | Stmicroelectronics, Inc. | Silver metallization by damascene method |
US6187672B1 (en) * | 1998-09-22 | 2001-02-13 | Conexant Systems, Inc. | Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing |
US6251789B1 (en) * | 1998-12-16 | 2001-06-26 | Texas Instruments Incorporated | Selective slurries for the formation of conductive structures |
US6245658B1 (en) * | 1999-02-18 | 2001-06-12 | Advanced Micro Devices, Inc. | Method of forming low dielectric semiconductor device with rigid, metal silicide lined interconnection system |
US6218282B1 (en) * | 1999-02-18 | 2001-04-17 | Advanced Micro Devices, Inc. | Method of forming low dielectric tungsten lined interconnection system |
US6020261A (en) * | 1999-06-01 | 2000-02-01 | Motorola, Inc. | Process for forming high aspect ratio circuit features |
-
2000
- 2000-12-11 EP EP00830810A patent/EP1213758B1/de not_active Expired - Lifetime
- 2000-12-11 DE DE60037255T patent/DE60037255D1/de not_active Expired - Lifetime
-
2001
- 2001-12-11 US US10/014,921 patent/US6475898B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP1213758B1 (de) | 2007-11-28 |
US6475898B2 (en) | 2002-11-05 |
US20020090810A1 (en) | 2002-07-11 |
EP1213758A1 (de) | 2002-06-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8332 | No legal effect for de |