DE60036777D1 - Gerät zur Signalsynchronisierung zwischen zwei Taktbereichen - Google Patents

Gerät zur Signalsynchronisierung zwischen zwei Taktbereichen

Info

Publication number
DE60036777D1
DE60036777D1 DE60036777T DE60036777T DE60036777D1 DE 60036777 D1 DE60036777 D1 DE 60036777D1 DE 60036777 T DE60036777 T DE 60036777T DE 60036777 T DE60036777 T DE 60036777T DE 60036777 D1 DE60036777 D1 DE 60036777D1
Authority
DE
Germany
Prior art keywords
domain
clock
synchronizer
data
synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60036777T
Other languages
English (en)
Other versions
DE60036777T2 (de
Inventor
Iain Robertson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE60036777D1 publication Critical patent/DE60036777D1/de
Application granted granted Critical
Publication of DE60036777T2 publication Critical patent/DE60036777T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE60036777T 2000-02-09 2000-02-09 Gerät zur Signalsynchronisierung zwischen zwei Taktbereichen Expired - Lifetime DE60036777T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP00301293A EP1124179B1 (de) 2000-02-09 2000-02-09 Gerät zur Signalsynchronisierung zwischen zwei Taktbereichen

Publications (2)

Publication Number Publication Date
DE60036777D1 true DE60036777D1 (de) 2007-11-29
DE60036777T2 DE60036777T2 (de) 2008-07-24

Family

ID=8172719

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60036777T Expired - Lifetime DE60036777T2 (de) 2000-02-09 2000-02-09 Gerät zur Signalsynchronisierung zwischen zwei Taktbereichen

Country Status (5)

Country Link
US (1) US6493818B2 (de)
EP (1) EP1124179B1 (de)
JP (1) JP2001265715A (de)
AT (1) ATE376211T1 (de)
DE (1) DE60036777T2 (de)

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US20040057548A1 (en) * 1994-03-18 2004-03-25 Silicon Integrated System Corp. Quasi-synchronous multi-stage event synchronization apparatus
ATE376211T1 (de) * 2000-02-09 2007-11-15 Texas Instruments Inc Gerät zur signalsynchronisierung zwischen zwei taktbereichen
US7027447B2 (en) * 2000-02-29 2006-04-11 Texas Instruments Incorporated Communications interface between clock domains with minimal latency
EP1276028A1 (de) * 2001-07-09 2003-01-15 Telefonaktiebolaget L M Ericsson (Publ) Einrichtung und Verfahren zum Detektieren von Statusindikationen
US7352836B1 (en) 2001-08-22 2008-04-01 Nortel Networks Limited System and method of cross-clock domain rate matching
DE10152195A1 (de) * 2001-10-23 2003-04-30 Koninkl Philips Electronics Nv Schaltungsanordnung
US7161999B2 (en) * 2002-01-02 2007-01-09 Intel Corporation Synchronizing data or signal transfer across clocked logic domains
US6922112B2 (en) * 2002-06-25 2005-07-26 Intel Corporation Clock signal generation and distribution via ring oscillators
US7149916B1 (en) * 2003-03-17 2006-12-12 Network Equipment Technologies, Inc. Method for time-domain synchronization across a bit-sliced data path design
US20040193931A1 (en) * 2003-03-26 2004-09-30 Akkerman Ryan L. System and method for transferring data from a first clock domain to a second clock domain
US7035983B1 (en) * 2003-04-25 2006-04-25 Advanced Micro Devices, Inc. System and method for facilitating communication across an asynchronous clock boundary
WO2004100000A1 (en) * 2003-05-09 2004-11-18 Koninklijke Philips Electronics N.V. Method for data signal transfer across different clock-domains
US7242737B2 (en) 2003-07-09 2007-07-10 International Business Machines Corporation System and method for data phase realignment
US7822105B2 (en) * 2003-09-02 2010-10-26 Sirf Technology, Inc. Cross-correlation removal of carrier wave jamming signals
EP1680686A1 (de) 2003-09-02 2006-07-19 Sirf Technology, Inc. Signalverarbeitungssystem für satellitenpositionierungssignale
JP4956713B2 (ja) * 2004-03-01 2012-06-20 エスティー‐エリクソン、ソシエテ、アノニム 互いに同期しない回路モジュールを備える回路
EP1601131B1 (de) * 2004-05-24 2007-07-11 STMicroelectronics Limited Asynchrones Mehrfachtaktsystem
MY137746A (en) * 2004-12-06 2009-03-31 Intel Corp System, apparatus, and method to increase information transfer across clock domains
JP4730051B2 (ja) * 2005-10-13 2011-07-20 日本電気株式会社 半導体ディジタル回路、ｆｉｆｏバッファ回路及びそれらに用いるデータ受け渡し方法
EP2039034A1 (de) * 2006-06-30 2009-03-25 Nxp B.V. Asynchroner daten-fifo für unterbrechungsfreien datenfluss
JP4758311B2 (ja) * 2006-09-14 2011-08-24 Ｏｋｉセミコンダクタ株式会社 非同期データ保持回路
KR100888597B1 (ko) * 2006-09-20 2009-03-16 삼성전자주식회사 메모리 인터페이스 제어 장치 및 제어 방법
US20080170649A1 (en) * 2007-01-11 2008-07-17 Harper Marcellus C Programmable Synchronizer/Terminator Method and Apparatus
US8131967B2 (en) * 2007-01-11 2012-03-06 International Business Machines Corporation Asynchronous data interface
US7966435B2 (en) * 2007-01-11 2011-06-21 International Business Machines Corporation Integrated circuit design structure for an asychronous data interface
US8867573B2 (en) * 2007-04-23 2014-10-21 Nokia Corporation Transferring data between asynchronous clock domains
US7934113B2 (en) * 2007-05-21 2011-04-26 Texas Instruments Incorporated Self-clearing asynchronous interrupt edge detect latching register
US7945875B2 (en) * 2007-06-14 2011-05-17 Texas Instruments Incorporated Methodology for hierarchy separation at asynchronous clock domain boundaries for multi-voltage optimization using design compiler
US7958285B1 (en) * 2007-07-12 2011-06-07 Oracle America, Inc. System and method to facilitate deterministic testing of data transfers between independent clock domains on a chip
ITMI20072450A1 (it) 2007-12-31 2009-07-01 St Microelectronics Srl Sistema di comunicazione tra un primo ed un secondo dispositivo sincroni temporalmente non correlati.
US8151075B2 (en) * 2010-01-22 2012-04-03 Freescale Semiconductor, Inc. Multiple access type memory and method of operation
US8868852B2 (en) * 2010-07-07 2014-10-21 Marvell World Trade Ltd. Interface management control systems and methods for non-volatile semiconductor memory
US9135168B2 (en) 2010-07-07 2015-09-15 Marvell World Trade Ltd. Apparatus and method for generating descriptors to reaccess a non-volatile semiconductor memory of a storage drive due to an error
US9141538B2 (en) 2010-07-07 2015-09-22 Marvell World Trade Ltd. Apparatus and method for generating descriptors to transfer data to and from non-volatile semiconductor memory of a storage drive
KR101849702B1 (ko) * 2011-07-25 2018-04-17 삼성전자주식회사 외부 인트린직 인터페이스
WO2013100976A1 (en) * 2011-12-28 2013-07-04 Intel Corporation Data transfer between asynchronous clock domains
GB2503472A (en) * 2012-06-27 2014-01-01 Nordic Semiconductor Asa Data transfer between clock domains following clock transition in destination domain
GB2505002B (en) * 2012-08-17 2014-09-24 Broadcom Corp Method and apparatus for transferring data from a first domain to a second domain
CN105610532B (zh) * 2014-11-11 2019-05-24 中兴通讯股份有限公司 信号的传输处理方法及装置、设备
US9680459B2 (en) * 2014-12-11 2017-06-13 Intel Corporation Edge-aware synchronization of a data signal
CN111262655B (zh) * 2020-01-15 2023-05-12 江苏方天电力技术有限公司 基于异步时钟的fpga万兆以太网数据高速发送方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3213345C2 (de) * 1982-04-08 1984-11-22 Siemens Ag, 1000 Berlin Und 8000 Muenchen Datenübertragungseinrichtung zwischen zwei asynchron gesteuerten Datenverarbeitungssystemen
US4873703A (en) * 1985-09-27 1989-10-10 Hewlett-Packard Company Synchronizing system
US4805198A (en) * 1987-05-19 1989-02-14 Crystal Semiconductor Corporation Clock multiplier/jitter attenuator
US6128715A (en) * 1997-05-30 2000-10-03 3Com Corporation Asynchronous transmit packet buffer
ATE376211T1 (de) * 2000-02-09 2007-11-15 Texas Instruments Inc Gerät zur signalsynchronisierung zwischen zwei taktbereichen

Also Published As

Publication number Publication date
US20010042219A1 (en) 2001-11-15
ATE376211T1 (de) 2007-11-15
EP1124179B1 (de) 2007-10-17
US6493818B2 (en) 2002-12-10
DE60036777T2 (de) 2008-07-24
EP1124179A1 (de) 2001-08-16
JP2001265715A (ja) 2001-09-28

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