DE60015424D1 - Phasenauswahlschaltung - Google Patents

Phasenauswahlschaltung

Info

Publication number
DE60015424D1
DE60015424D1 DE60015424T DE60015424T DE60015424D1 DE 60015424 D1 DE60015424 D1 DE 60015424D1 DE 60015424 T DE60015424 T DE 60015424T DE 60015424 T DE60015424 T DE 60015424T DE 60015424 D1 DE60015424 D1 DE 60015424D1
Authority
DE
Germany
Prior art keywords
phase
tap
selection circuit
multiplexing
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60015424T
Other languages
English (en)
Other versions
DE60015424T2 (de
Inventor
Greg Warwar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsemi Communications Inc
Original Assignee
Vitesse Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vitesse Semiconductor Corp filed Critical Vitesse Semiconductor Corp
Publication of DE60015424D1 publication Critical patent/DE60015424D1/de
Application granted granted Critical
Publication of DE60015424T2 publication Critical patent/DE60015424T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)
  • Stereo-Broadcasting Methods (AREA)
  • Circuits Of Receivers In General (AREA)
  • Analogue/Digital Conversion (AREA)
DE60015424T 1999-03-09 2000-03-09 Phasenauswahlschaltung Expired - Fee Related DE60015424T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/265,725 US6229344B1 (en) 1999-03-09 1999-03-09 Phase selection circuit
US265725 1999-03-09

Publications (2)

Publication Number Publication Date
DE60015424D1 true DE60015424D1 (de) 2004-12-09
DE60015424T2 DE60015424T2 (de) 2005-10-27

Family

ID=23011645

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60015424T Expired - Fee Related DE60015424T2 (de) 1999-03-09 2000-03-09 Phasenauswahlschaltung

Country Status (6)

Country Link
US (1) US6229344B1 (de)
EP (1) EP1049257B1 (de)
AT (1) ATE281710T1 (de)
DE (1) DE60015424T2 (de)
DK (1) DK1049257T3 (de)
ES (1) ES2232380T3 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6233294B1 (en) * 1999-08-17 2001-05-15 Richard Bowers Method and apparatus for accomplishing high bandwidth serial communication between semiconductor devices
AU2002228866A1 (en) * 2000-11-13 2002-05-21 Primarion, Inc. High bandwidth multi-phase clock selector with continuous phase output
US20030210758A1 (en) * 2002-04-30 2003-11-13 Realtek Semiconductor Corp. Recovered clock generator with high phase resolution and recovered clock generating method
KR100486276B1 (ko) * 2002-11-05 2005-04-29 삼성전자주식회사 입력되는 두 클럭의 인터폴레이팅에 의하여 지연량의차이를 조절할 수 있는 지연된 탭신호들을 발생하는 회로
EP1473828A1 (de) * 2003-04-30 2004-11-03 STMicroelectronics S.r.l. Phasendetektor und dazugehöriges Verfahren zum Erzeugen eines die Phasenverschiebung darstellenden Signals
US8155018B2 (en) * 2004-03-03 2012-04-10 Qualcomm Atheros, Inc. Implementing location awareness in WLAN devices
US7046072B2 (en) * 2004-03-03 2006-05-16 Atheros Communications, Inc. Commutating phase selector
US8754678B1 (en) * 2013-03-15 2014-06-17 Analog Devices, Inc. Apparatus and methods for invertible sine-shaping for phase interpolation
US8957704B1 (en) * 2013-09-06 2015-02-17 Synopsys, Inc. High speed phase selector with a glitchless output used in phase locked loop applications

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5034967A (en) * 1988-11-14 1991-07-23 Datapoint Corporation Metastable-free digital synchronizer with low phase error
US5485490A (en) * 1992-05-28 1996-01-16 Rambus, Inc. Method and circuitry for clock synchronization
US5355035A (en) * 1993-01-08 1994-10-11 Vora Madhukar B High speed BICMOS switches and multiplexers
US5561692A (en) * 1993-12-09 1996-10-01 Northern Telecom Limited Clock phase shifting method and apparatus
US5475344A (en) * 1994-02-22 1995-12-12 The Board Of Trustees Of The Leland Stanford Junior University Multiple interconnected ring oscillator circuit
US5570294A (en) * 1994-03-11 1996-10-29 Advanced Micro Devices Circuit configuration employing a compare unit for testing variably controlled delay units
US5552745A (en) * 1994-09-21 1996-09-03 International Business Machines Corporation Self-resetting CMOS multiplexer with static output driver
US5644604A (en) * 1994-11-14 1997-07-01 Hal Computer Systems, Inc. Digital phase selector system and method
JPH08321827A (ja) * 1995-03-20 1996-12-03 Fujitsu Ltd データ識別装置及びこれを用いた光受信器
DE69630576T2 (de) * 1995-07-21 2004-09-16 Koninklijke Philips Electronics N.V. Vorrichtung zur drahtlosen digitalen kommunikation und pulsformungsnetzwerk
US6034570A (en) * 1997-06-27 2000-03-07 Vitesse Semiconductor Corporation Gallium arsenide voltage-controlled oscillator and oscillator delay cell

Also Published As

Publication number Publication date
ES2232380T3 (es) 2005-06-01
US6229344B1 (en) 2001-05-08
EP1049257A3 (de) 2002-01-02
ATE281710T1 (de) 2004-11-15
DK1049257T3 (da) 2005-03-14
DE60015424T2 (de) 2005-10-27
EP1049257B1 (de) 2004-11-03
EP1049257A2 (de) 2000-11-02

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KR100486276B1 (ko) 입력되는 두 클럭의 인터폴레이팅에 의하여 지연량의차이를 조절할 수 있는 지연된 탭신호들을 발생하는 회로

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee