DE60006720D1 - Sdram mit eingangsmaskierung - Google Patents

Sdram mit eingangsmaskierung

Info

Publication number
DE60006720D1
DE60006720D1 DE60006720T DE60006720T DE60006720D1 DE 60006720 D1 DE60006720 D1 DE 60006720D1 DE 60006720 T DE60006720 T DE 60006720T DE 60006720 T DE60006720 T DE 60006720T DE 60006720 D1 DE60006720 D1 DE 60006720D1
Authority
DE
Germany
Prior art keywords
sdram
input masking
masking
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60006720T
Other languages
English (en)
Other versions
DE60006720T2 (de
Inventor
R Hanson
Toshiaki Kirihata
Gerhard Mueller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
International Business Machines Corp
Original Assignee
Infineon Technologies AG
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG, International Business Machines Corp filed Critical Infineon Technologies AG
Publication of DE60006720D1 publication Critical patent/DE60006720D1/de
Application granted granted Critical
Publication of DE60006720T2 publication Critical patent/DE60006720T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE60006720T 1999-12-08 2000-12-04 Sdram mit eingangsmaskierung Expired - Fee Related DE60006720T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/456,588 US6240043B1 (en) 1999-12-08 1999-12-08 SDRAM with a maskable input
US456588 1999-12-08
PCT/US2000/032845 WO2001043134A1 (en) 1999-12-08 2000-12-04 A sdram with a maskable input

Publications (2)

Publication Number Publication Date
DE60006720D1 true DE60006720D1 (de) 2003-12-24
DE60006720T2 DE60006720T2 (de) 2004-09-23

Family

ID=23813371

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60006720T Expired - Fee Related DE60006720T2 (de) 1999-12-08 2000-12-04 Sdram mit eingangsmaskierung

Country Status (6)

Country Link
US (1) US6240043B1 (de)
EP (1) EP1242996B1 (de)
KR (1) KR100459798B1 (de)
DE (1) DE60006720T2 (de)
TW (1) TW498344B (de)
WO (1) WO2001043134A1 (de)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5796673A (en) * 1994-10-06 1998-08-18 Mosaid Technologies Incorporated Delay locked loop implementation in a synchronous dynamic random access memory
JP2001035153A (ja) * 1999-07-23 2001-02-09 Fujitsu Ltd 半導体記憶装置
DE10156749B4 (de) * 2001-11-19 2007-05-10 Infineon Technologies Ag Speicher, Prozessorsystem und Verfahren zum Durchführen von Schreiboperationen auf einen Speicherbereich
US7685456B1 (en) 2003-07-30 2010-03-23 Marvell Israel (Misl) Ltd. DDR interface bus control
US7345933B1 (en) 2005-01-13 2008-03-18 Marvell Semiconductor Israel Ltd. Qualified data strobe signal for double data rate memory controller module
US7397727B2 (en) * 2005-12-22 2008-07-08 Infineon Technologies Ag Write burst stop function in low power DDR sDRAM
KR100712546B1 (ko) 2006-01-12 2007-05-02 삼성전자주식회사 동기식 반도체 메모리 장치의 기입 데이터 마스크 신호발생 회로 및 기입 데이터 마스크 신호 발생 방법
US8257463B2 (en) * 2006-01-23 2012-09-04 Avx Corporation Capacitor anode formed from flake powder
US7636250B2 (en) * 2006-07-17 2009-12-22 Qimonda North America Corp. Random access memory that selectively provides data to amplifiers
US7830726B2 (en) 2008-09-30 2010-11-09 Seagate Technology Llc Data storage using read-mask-write operation
US20100085685A1 (en) * 2008-10-06 2010-04-08 Avx Corporation Capacitor Anode Formed From a Powder Containing Coarse Agglomerates and Fine Agglomerates
KR20100101449A (ko) * 2009-03-09 2010-09-17 삼성전자주식회사 메모리 장치, 그것의 마스크 데이터 전송 방법 및 입력 데이터 정렬 방법
KR101201861B1 (ko) 2010-11-09 2012-11-15 에스케이하이닉스 주식회사 반도체 메모리 장치의 데이터 마스크 동작 테스트 회로
KR102017808B1 (ko) * 2013-12-31 2019-09-03 에스케이하이닉스 주식회사 데이터 처리 장치 및 데이터 처리 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384745A (en) * 1992-04-27 1995-01-24 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device
JPH07130166A (ja) * 1993-09-13 1995-05-19 Mitsubishi Electric Corp 半導体記憶装置および同期型半導体記憶装置
KR0165159B1 (ko) * 1994-07-28 1999-02-01 사또 후미오 반도체 기억 장치
US5657287A (en) * 1995-05-31 1997-08-12 Micron Technology, Inc. Enhanced multiple block writes to adjacent blocks of memory using a sequential counter
US5655105A (en) * 1995-06-30 1997-08-05 Micron Technology, Inc. Method and apparatus for multiple latency synchronous pipelined dynamic random access memory

Also Published As

Publication number Publication date
TW498344B (en) 2002-08-11
EP1242996B1 (de) 2003-11-19
KR20030009331A (ko) 2003-01-29
KR100459798B1 (ko) 2004-12-03
EP1242996A1 (de) 2002-09-25
US6240043B1 (en) 2001-05-29
DE60006720T2 (de) 2004-09-23
WO2001043134A1 (en) 2001-06-14

Similar Documents

Publication Publication Date Title
DE60019770D1 (de) Photochrome naphtopyranen
DE60044873D1 (de) Orientierte biopolymermembrane
DE60144474D1 (de) Variabler modenmittler
DE60023998D1 (de) Immunoassay
DE69905427T2 (de) Ausgedehnte Beleuchtungseinrichtung
PT1341791E (pt) Imidazoquinolinas substituidas com tioeter
ID28990A (id) Herbisida-herbisida dengan urea aminofenilsulfonil asilasi
DE60022965D1 (de) Saugfähiger Gegenstand
DE60018495D1 (de) Tamponeinführhilfe
ID28773A (id) Penunjukan-tanah dengan tekanan-sama
DE60018142D1 (de) Tamponapplikator
DE50000494D1 (de) Funktionsträgeranordnung
NO20030917D0 (no) Anvendelse
DE50106159D1 (de) Kochfeld
DE60006720D1 (de) Sdram mit eingangsmaskierung
ES1044448Y (es) Auto-aplicador de vendaje
DE60025251D1 (de) Tamponapplikator
DK1058069T3 (da) Absorber
DE60143148D1 (de) En mit honigwaben
DE50109740D1 (de) Einbaukochmulde
DE69915065D1 (de) Reissnadel
NO20020869D0 (no) Absorberende gjenstand
ID25567A (id) Ulir-jepit dengan bahu-puntir
DE60132244D1 (de) Mikrowellenverstärker mit bypass-segment
DE60025033D1 (de) Kochplatte

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

Owner name: INTERNATIONAL BUSINESS MACHINES CORP., ARMONK,, US

8339 Ceased/non-payment of the annual fee