DE60001927D1 - Verfahren und vorrichtung zum schutz von konfigurationsdateneigentum für programmierbare logische vorrichtungen - Google Patents

Verfahren und vorrichtung zum schutz von konfigurationsdateneigentum für programmierbare logische vorrichtungen

Info

Publication number
DE60001927D1
DE60001927D1 DE60001927T DE60001927T DE60001927D1 DE 60001927 D1 DE60001927 D1 DE 60001927D1 DE 60001927 T DE60001927 T DE 60001927T DE 60001927 T DE60001927 T DE 60001927T DE 60001927 D1 DE60001927 D1 DE 60001927D1
Authority
DE
Germany
Prior art keywords
configuration data
logical devices
programmable logical
data property
protecting configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60001927T
Other languages
English (en)
Other versions
DE60001927T2 (de
Inventor
M Trimberger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Application granted granted Critical
Publication of DE60001927D1 publication Critical patent/DE60001927D1/de
Publication of DE60001927T2 publication Critical patent/DE60001927T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17768—Structural details of configuration resources for security
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0625—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0643—Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H04L9/3236—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using cryptographic hash functions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
DE60001927T 1999-02-19 2000-01-19 Verfahren und vorrichtung zum schutz von konfigurationsdateneigentum für programmierbare logische vorrichtungen Expired - Lifetime DE60001927T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US253401 1999-02-19
US09/253,401 US6654889B1 (en) 1999-02-19 1999-02-19 Method and apparatus for protecting proprietary configuration data for programmable logic devices
PCT/US2000/001398 WO2000049717A2 (en) 1999-02-19 2000-01-19 Method and apparatus for protecting proprietary configuration data for programmable logic devices

Publications (2)

Publication Number Publication Date
DE60001927D1 true DE60001927D1 (de) 2003-05-08
DE60001927T2 DE60001927T2 (de) 2004-02-12

Family

ID=22960124

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60001927T Expired - Lifetime DE60001927T2 (de) 1999-02-19 2000-01-19 Verfahren und vorrichtung zum schutz von konfigurationsdateneigentum für programmierbare logische vorrichtungen

Country Status (5)

Country Link
US (1) US6654889B1 (de)
EP (1) EP1153480B1 (de)
JP (1) JP2002537709A (de)
DE (1) DE60001927T2 (de)
WO (1) WO2000049717A2 (de)

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Also Published As

Publication number Publication date
WO2000049717A3 (en) 2000-11-02
EP1153480A2 (de) 2001-11-14
US6654889B1 (en) 2003-11-25
DE60001927T2 (de) 2004-02-12
EP1153480B1 (de) 2003-04-02
JP2002537709A (ja) 2002-11-05
WO2000049717A2 (en) 2000-08-24

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