US3849760A - Multi-dimensional pattern recognition processor - Google Patents
Multi-dimensional pattern recognition processor Download PDFInfo
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- US3849760A US3849760A US00270873A US27087372A US3849760A US 3849760 A US3849760 A US 3849760A US 00270873 A US00270873 A US 00270873A US 27087372 A US27087372 A US 27087372A US 3849760 A US3849760 A US 3849760A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V10/00—Arrangements for image or video recognition or understanding
- G06V10/40—Extraction of image or video features
- G06V10/48—Extraction of image or video features by mapping characteristic values of the pattern into a parameter space, e.g. Hough transformation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V10/00—Arrangements for image or video recognition or understanding
- G06V10/70—Arrangements for image or video recognition or understanding using pattern recognition or machine learning
- G06V10/74—Image or video pattern matching; Proximity measures in feature spaces
- G06V10/75—Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video features; Coarse-fine approaches, e.g. multi-scale approaches; using context analysis; Selection of dictionaries
- G06V10/751—Comparing pixel values or logical combinations thereof, or feature values having positional relevance, e.g. template matching
- G06V10/7515—Shifting the patterns to accommodate for positional errors
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- SHEET 09 my 20 PEG. l2
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- Computer Vision & Pattern Recognition (AREA)
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- General Health & Medical Sciences (AREA)
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Abstract
A multi-dimensional pattern recognition processor comprising a pattern data register unit for storing information of a multidimensional original pattern, a weight register unit for applying weight information to the original pattern information, and a filtering logic arithmetic unit for carrying out predetermined arithmetic operations (filtering logic) on the original pattern information and weight information stored in and supplied from the respective register units. In the processor, various weight information are employed so as to carry out (1) space coordinate transformation such as rotation, expansion or contraction of the multi-dimensional original pattern, (2) operation for seeking the correlation between the multi-dimensional original pattern and a standard pattern, (3) detection of the geometrical features of the multi-dimensional original pattern, or (4) extraction of the features as to the color and tone of the multi-dimensional original pattern.
Description
United States Patent 1191 I Endou et al.
[451 Nov. 19, 1974 MULTl-DIMENSIONAL PATTERN RECOGNITION PROCESSOR Primary Examiner-Gareth D. Shaw [75] Inventors: Hirohide Endou, Kokubunji; Jim Assistant Examiner-"Joseph Thesz Kawasaki; Yoshi Fujimoto, both of Attorney, Agent, or F1rmCra1g & Antonell1 l-lachioji; Keiichi Nakane, Kokubunji; Yoshiaki Kitazume, [57] ABSTRACT Sayama, all of Japan A multi-dimensional pattern recognition processor comprising a pattern data register unit for storing in- [73] Asslgnee Hnachl Tokyo Japan formation of a multi-dimensional original pattern, a [22] Filed: July 11, 1972 weight register unit for applying weight information to the original pattern information, and a filtering logic [211 Appl' 270873 arithmetic unit for carrying out predetermined arithmetic operations (filtering logic) on the original pat- [30] Foreign Application Priority Data tern information and weight information stored in and July 12, 1971 Japan .j 46-51609 Supplied from the respective register the Nov. 10, 1971 Japan I I i 46 89O22 cessor, various weight information are employed so as Apr. 28, 1972 Japan 47-42217 to carry out (1) space comdinate transformation Such as rotation, expansion or contraction of the multi- 52 us. 01. 340/1463 11 dimensional Original P (2) Operation for Seeking 51 1m. (:1. G06k 9/00 the correlation between the multidimensional Original [58] Field 61 Search... 340/1463 H, 146.3 Q, 172.5 Pattern and Standard Pattern, (3) detection of the g geometrical features'of the multi-dimensional original 5 References Cited pattern, or (4) extraction of the features as to the UNITED STATES PATENTS color and tone of the multi-dimensional original patt 3,036,775 5/1962 McDermid et al....; 340/1463 Q er 3, 14,736 10 1971 McLaughlin 340 1463 o 7 Claims, 37 Drawing Figures BUFFER (i: MEMORY (j:
I3 I MASK DATA REGISTER blblER RtGlblE ooNTRoL UNIT ('4 FILTERING LOGIC ARITHMETIC UNIT NON-LINEAR ARITHMETIC UNIT PAIENTEL HUV 1 9 I974 sum 02 0F 20 F l G. 2
I BUFFER MEMORY :2)
h r? JO K8 ll lo I3 I MASK DATA (so REGISTER REGISTER REGISTER CONTROL UNIT FILTERING LOGIC ARITHMETIC UNIT NON-LINEAR ARITHMETIC UNIT PATENTE RSV 1 9l974 sum 03 car zo FIG.
PATENTL 513V 1 9 I974 sum 08 or 2o FIG.
Y 2 000 Z WijDii FIG.
r-lll 6 w M A O O O o 0 o O O b 8 .l l q 4 4 I I. I M 4 W F r 0 O l.- O O o 0 l PATENTELrzsvx 9:974 849,760
SHEET 09 my 20 PEG. l2
0 o o 0 0 O o o o 0 0 0 o o o o O o O 0 o o O o '2 0 O 0 o o o 0 0 o o o o l O o 0 o 0 o I O O 0 Q o O O O O 0 o o I O o 0 O 0 o O o O PATENTE am: 1 9mm sum 10 or 20 FIGQI4 PATENTEL 253V 1 9 I974 sum 12 or 20 FIG. I?
p M =l 00.oo 00o00000000o M00000000 00o0oo00 l ooooooooooooo ooo koooooooooooooooo Hoooooooooooooooo. oooooooooooooooo 9.0000000000000000 80000000000000000 7 0 000000000000000 60000000000000000 50000000000000000 4 0000000000000000 30000000000000000 20000000000000000 0000000000000000 00000000000000000 O 23456789m 23 my D(xy) R(Xo yo) HDVISISN 3,849,760
FIG. 20c
PAH-INTEL 213V 1 9 I974 sum "17 or 2 FacsQ24 Ol2345678 Ol234567 .I II
PATENTE HUVI 9 1974 sum '18 or 2o FIG. 25
lOOOOO00- O 0 O 0 0 O 0 o o 0 o O O 0 0 o 00 0O 0O 0o 0O 0O O0 O0 O O O O 0 O O O O O O O O O O 0 0 0 O O O O O O O00 O00 O00 000 000 000 O00 00 O O 0 O o O O O o 0 O O 0 0 0 0 FIG. 26
G v F PATENTEL nun 91974 3 49 ,7 6 6 sum =19 or 2 FIG. 28
FROM F MASK REGISTER 8 PATTERN DATA REGISTERS 9, IO, |2.
RESULTANT INFORMATION
Claims (7)
1. A multi-dimensional pattern recognition processor comprising a pattern data register unit for storing information of individual picture elements of a multi-dimensional original pattern, a mask register unit for designating a multi-dimensional weight information pattern applied to the pattern information of the individual picture elements of the original pattern, a plurality of multiplier groups for simultaneously carrying out the multiplication on all the picture elements of the original pattern such that pattern information signals representative of the picture elements of the original pattern derived from said pattern data register unit are multiplied by weight information signals derived from the corresponding picture element portions of said mask register unit, and a plurality of adders each associated with one of said multiplier groups for carrying out the addition of the results of multiplication by said multiplier groups, wherein weight information stored in said mask register unit is changed to various forms so that said original pattern information can be suitably processed depending on said changed weight information.
2. A multi-dimensional pattern recognition processor as claimed in claim 1, wherein a non-linear arithmetic unit is additionally provided for selecting solely the signals having a level higher than a predetermined threshold value from the output signals of said adders.
3. A multi-dimensional pattern recognition processor as claimed in claim 1, wherein said weight information pattern comprises a plurality of picture elements lying along one diagonal of a square and lying along a partial circle drawn around one of the ends of said diagonal so as to pass through the center of said square, and a plurality of picture elements adjoining to said picture elements along said diagonal and said partial circle, said partial circle being defined in the area of said square.
4. A multi-dimensional pattern recognition processor as claimed in claim 1, wherein said weight information pattern comprises a plurality of picture elements arranged in the shape of a square with at least one picture element added to a side of said square.
5. A multi-dimensional pattern recognition processor as claimed in claim 1, wherein said weight information pattern comprises a plurality of picture elements arranged in a square with at least one picture element added to each of two sides of the square and at least one additional picture element added to at least one corner of the square in the direction of a diagonal of the square.
6. A multi-dimensional pattern recognition processor comprising a pattern data register unit for storing information of indIvidual picture elements of a multi-dimensional original pattern, a mask register unit for designating the weight applied to the pattern information of the individual picture elements of the original pattern, a plurality of hybrid multiplier groups connected to said register units for computing the product of two input signals representative of a multiplier and a multiplicant one of which is a digital signal and the other of which is an analog signal, a plurality of analog adder groups each connected to one of said hybrid multiplier groups for carrying out the addition of an addend and a summand both of which are analog signals, and a group of analog to digital converters each converting the analog output signal of one of said adder groups into a digital signal, wherein the weight information stored in said mask register unit is changed to various forms so that said pattern information can be suitably processed depending on said changed weight information.
7. A multi-dimensional pattern recognition processor as claimed in claim 6, wherein a non-linear arithmetic unit is connected between said analog adder groups and said analog to digital converter group so as to select solely the analog signals having a level higher than a predetermined threshold value from the analog output signals of said analog adder groups.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP46051609A JPS52343B1 (en) | 1971-07-12 | 1971-07-12 | |
JP46089022A JPS5131135B2 (en) | 1971-11-10 | 1971-11-10 | |
JP4221772A JPS5416181B2 (en) | 1972-04-28 | 1972-04-28 |
Publications (1)
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US3849760A true US3849760A (en) | 1974-11-19 |
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US00270873A Expired - Lifetime US3849760A (en) | 1971-07-12 | 1972-07-11 | Multi-dimensional pattern recognition processor |
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Cited By (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3967243A (en) * | 1973-07-09 | 1976-06-29 | Kabushiki Kaisha Ricoh | Character pattern normalization method and apparatus for optical character recognition system |
US4168488A (en) * | 1977-09-12 | 1979-09-18 | International Business Machines Corporation | Image rotation apparatus |
FR2474722A1 (en) * | 1980-01-15 | 1981-07-31 | Goodyear Aerospace Corp | Digital video correlator for e,g, aircraft guidance system - has single-bit correlators for comparing digitised valves of live and reference images in shifting network |
US4318080A (en) * | 1976-12-16 | 1982-03-02 | Hajime Industries, Ltd. | Data processing system utilizing analog memories having different data processing characteristics |
US4395698A (en) * | 1980-08-15 | 1983-07-26 | Environmental Research Institute Of Michigan | Neighborhood transformation logic circuitry for an image analyzer system |
EP0092381A2 (en) * | 1982-04-15 | 1983-10-26 | Kabushiki Kaisha Toshiba | Pattern features extracting apparatus and method and pattern recognition system |
US4644488A (en) * | 1983-10-12 | 1987-02-17 | California Institute Of Technology | Pipeline active filter utilizing a booth type multiplier |
US4667295A (en) * | 1982-12-21 | 1987-05-19 | Preston Jr Kendall | Logical transform image processor |
US4723298A (en) * | 1985-03-27 | 1988-02-02 | Fingermatrix, Inc. | Image compression technique |
US4736448A (en) * | 1984-03-31 | 1988-04-05 | Kabushiki Kaisha Toshiba | Spatial filter |
US5067019A (en) * | 1989-03-31 | 1991-11-19 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Programmable remapper for image processing |
US5892961A (en) * | 1995-02-17 | 1999-04-06 | Xilinx, Inc. | Field programmable gate array having programming instructions in the configuration bitstream |
US6028445A (en) * | 1997-12-30 | 2000-02-22 | Xilinx, Inc. | Decoder structure and method for FPGA configuration |
US6069489A (en) * | 1998-08-04 | 2000-05-30 | Xilinx, Inc. | FPGA having fast configuration memory data readback |
US6097210A (en) * | 1998-08-04 | 2000-08-01 | Xilinx, Inc. | Multiplexer array with shifted input traces |
US6137307A (en) * | 1998-08-04 | 2000-10-24 | Xilinx, Inc. | Structure and method for loading wide frames of data from a narrow input bus |
US6160418A (en) * | 1999-01-14 | 2000-12-12 | Xilinx, Inc. | Integrated circuit with selectively disabled logic blocks |
US6172520B1 (en) | 1997-12-30 | 2001-01-09 | Xilinx, Inc. | FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA |
US6205574B1 (en) | 1998-07-28 | 2001-03-20 | Xilinx, Inc. | Method and system for generating a programming bitstream including identification bits |
US6301695B1 (en) | 1999-01-14 | 2001-10-09 | Xilinx, Inc. | Methods to securely configure an FPGA using macro markers |
US6305005B1 (en) | 1999-01-14 | 2001-10-16 | Xilinx, Inc. | Methods to securely configure an FPGA using encrypted macros |
US6324676B1 (en) | 1999-01-14 | 2001-11-27 | Xilinx, Inc. | FPGA customizable to accept selected macros |
US6357037B1 (en) | 1999-01-14 | 2002-03-12 | Xilinx, Inc. | Methods to securely configure an FPGA to accept selected macros |
US6400996B1 (en) | 1999-02-01 | 2002-06-04 | Steven M. Hoffberg | Adaptive pattern recognition based control system and method |
US6418424B1 (en) | 1991-12-23 | 2002-07-09 | Steven M. Hoffberg | Ergonomic man-machine interface incorporating adaptive pattern recognition based control system |
US6654889B1 (en) | 1999-02-19 | 2003-11-25 | Xilinx, Inc. | Method and apparatus for protecting proprietary configuration data for programmable logic devices |
EP1011064A3 (en) * | 1998-11-30 | 2005-06-22 | Canon Kabushiki Kaisha | Image pattern detection method and apparatus |
EP1600883A2 (en) | 2004-05-28 | 2005-11-30 | Matsushita Electric Works, Ltd. | Object recognition system |
US6996713B1 (en) | 2002-03-29 | 2006-02-07 | Xilinx, Inc. | Method and apparatus for protecting proprietary decryption keys for programmable logic devices |
US20060136110A1 (en) * | 2004-12-20 | 2006-06-22 | Caterpillar Inc. | Adaptive vibration management system for a work machine |
US7134025B1 (en) | 2002-03-29 | 2006-11-07 | Xilinx, Inc. | Methods and circuits for preventing the overwriting of memory frames in programmable logic devices |
US7242988B1 (en) | 1991-12-23 | 2007-07-10 | Linda Irene Hoffberg | Adaptive pattern recognition based controller apparatus and method and human-factored interface therefore |
US20100100691A1 (en) * | 2008-10-18 | 2010-04-22 | Micron Technology, Inc. | Indirect Register Access Method and System |
US20110156896A1 (en) * | 1999-02-01 | 2011-06-30 | Hoffberg Steven M | Internet appliance system and method |
US7974714B2 (en) | 1999-10-05 | 2011-07-05 | Steven Mark Hoffberg | Intelligent electronic appliance system and method |
US8046313B2 (en) | 1991-12-23 | 2011-10-25 | Hoffberg Steven M | Ergonomic man-machine interface incorporating adaptive pattern recognition based control system |
US8364136B2 (en) | 1999-02-01 | 2013-01-29 | Steven M Hoffberg | Mobile system, a method of operating mobile system and a non-transitory computer readable medium for a programmable control of a mobile system |
US20140115002A1 (en) * | 2012-10-23 | 2014-04-24 | Liebherr-Werk Nenzing Gmbh | Method for monitoring a number of machines and monitoring system |
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US10419541B2 (en) | 2008-11-26 | 2019-09-17 | Free Stream Media Corp. | Remotely control devices over a network without authentication or registration |
US10567823B2 (en) | 2008-11-26 | 2020-02-18 | Free Stream Media Corp. | Relevant advertisement generation based on a user operating a client device communicatively coupled with a networked media device |
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Cited By (95)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3967243A (en) * | 1973-07-09 | 1976-06-29 | Kabushiki Kaisha Ricoh | Character pattern normalization method and apparatus for optical character recognition system |
US4318080A (en) * | 1976-12-16 | 1982-03-02 | Hajime Industries, Ltd. | Data processing system utilizing analog memories having different data processing characteristics |
US4168488A (en) * | 1977-09-12 | 1979-09-18 | International Business Machines Corporation | Image rotation apparatus |
FR2474722A1 (en) * | 1980-01-15 | 1981-07-31 | Goodyear Aerospace Corp | Digital video correlator for e,g, aircraft guidance system - has single-bit correlators for comparing digitised valves of live and reference images in shifting network |
US4395698A (en) * | 1980-08-15 | 1983-07-26 | Environmental Research Institute Of Michigan | Neighborhood transformation logic circuitry for an image analyzer system |
EP0092381A2 (en) * | 1982-04-15 | 1983-10-26 | Kabushiki Kaisha Toshiba | Pattern features extracting apparatus and method and pattern recognition system |
EP0092381A3 (en) * | 1982-04-15 | 1985-11-06 | Kabushiki Kaisha Toshiba | Pattern features extracting apparatus and method |
US4667295A (en) * | 1982-12-21 | 1987-05-19 | Preston Jr Kendall | Logical transform image processor |
US4644488A (en) * | 1983-10-12 | 1987-02-17 | California Institute Of Technology | Pipeline active filter utilizing a booth type multiplier |
US4736448A (en) * | 1984-03-31 | 1988-04-05 | Kabushiki Kaisha Toshiba | Spatial filter |
US4723298A (en) * | 1985-03-27 | 1988-02-02 | Fingermatrix, Inc. | Image compression technique |
US5067019A (en) * | 1989-03-31 | 1991-11-19 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Programmable remapper for image processing |
US8046313B2 (en) | 1991-12-23 | 2011-10-25 | Hoffberg Steven M | Ergonomic man-machine interface incorporating adaptive pattern recognition based control system |
US6418424B1 (en) | 1991-12-23 | 2002-07-09 | Steven M. Hoffberg | Ergonomic man-machine interface incorporating adaptive pattern recognition based control system |
US8892495B2 (en) | 1991-12-23 | 2014-11-18 | Blanding Hovenweep, Llc | Adaptive pattern recognition based controller apparatus and method and human-interface therefore |
US7242988B1 (en) | 1991-12-23 | 2007-07-10 | Linda Irene Hoffberg | Adaptive pattern recognition based controller apparatus and method and human-factored interface therefore |
US5892961A (en) * | 1995-02-17 | 1999-04-06 | Xilinx, Inc. | Field programmable gate array having programming instructions in the configuration bitstream |
US6172520B1 (en) | 1997-12-30 | 2001-01-09 | Xilinx, Inc. | FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA |
US6028445A (en) * | 1997-12-30 | 2000-02-22 | Xilinx, Inc. | Decoder structure and method for FPGA configuration |
US6205574B1 (en) | 1998-07-28 | 2001-03-20 | Xilinx, Inc. | Method and system for generating a programming bitstream including identification bits |
US6154048A (en) * | 1998-08-04 | 2000-11-28 | Xilinx, Inc. | Structure and method for loading narrow frames of data from a wide input bus |
US6201406B1 (en) | 1998-08-04 | 2001-03-13 | Xilinx, Inc. | FPGA configurable by two types of bitstreams |
US6137307A (en) * | 1998-08-04 | 2000-10-24 | Xilinx, Inc. | Structure and method for loading wide frames of data from a narrow input bus |
US6097210A (en) * | 1998-08-04 | 2000-08-01 | Xilinx, Inc. | Multiplexer array with shifted input traces |
US6069489A (en) * | 1998-08-04 | 2000-05-30 | Xilinx, Inc. | FPGA having fast configuration memory data readback |
US6323681B1 (en) | 1998-08-04 | 2001-11-27 | Xilinx, Inc. | Circuits and methods for operating a multiplexer array |
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US6305005B1 (en) | 1999-01-14 | 2001-10-16 | Xilinx, Inc. | Methods to securely configure an FPGA using encrypted macros |
US6160418A (en) * | 1999-01-14 | 2000-12-12 | Xilinx, Inc. | Integrated circuit with selectively disabled logic blocks |
US6381732B1 (en) | 1999-01-14 | 2002-04-30 | Xilinx, Inc. | FPGA customizable to accept selected macros |
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US6301695B1 (en) | 1999-01-14 | 2001-10-09 | Xilinx, Inc. | Methods to securely configure an FPGA using macro markers |
US6357037B1 (en) | 1999-01-14 | 2002-03-12 | Xilinx, Inc. | Methods to securely configure an FPGA to accept selected macros |
US8364136B2 (en) | 1999-02-01 | 2013-01-29 | Steven M Hoffberg | Mobile system, a method of operating mobile system and a non-transitory computer readable medium for a programmable control of a mobile system |
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US10361802B1 (en) | 1999-02-01 | 2019-07-23 | Blanding Hovenweep, Llc | Adaptive pattern recognition based control system and method |
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US6400996B1 (en) | 1999-02-01 | 2002-06-04 | Steven M. Hoffberg | Adaptive pattern recognition based control system and method |
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US20110156896A1 (en) * | 1999-02-01 | 2011-06-30 | Hoffberg Steven M | Internet appliance system and method |
US6654889B1 (en) | 1999-02-19 | 2003-11-25 | Xilinx, Inc. | Method and apparatus for protecting proprietary configuration data for programmable logic devices |
US7974714B2 (en) | 1999-10-05 | 2011-07-05 | Steven Mark Hoffberg | Intelligent electronic appliance system and method |
US7200235B1 (en) | 2002-03-29 | 2007-04-03 | Xilinx, Inc. | Error-checking and correcting decryption-key memory for programmable logic devices |
US7389429B1 (en) | 2002-03-29 | 2008-06-17 | Xilinx, Inc. | Self-erasing memory for protecting decryption keys and proprietary configuration data |
US7373668B1 (en) | 2002-03-29 | 2008-05-13 | Xilinx, Inc. | Methods and circuits for protecting proprietary configuration data for programmable logic devices |
US7366306B1 (en) | 2002-03-29 | 2008-04-29 | Xilinx, Inc. | Programmable logic device that supports secure and non-secure modes of decryption-key access |
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US7162644B1 (en) | 2002-03-29 | 2007-01-09 | Xilinx, Inc. | Methods and circuits for protecting proprietary configuration data for programmable logic devices |
US7134025B1 (en) | 2002-03-29 | 2006-11-07 | Xilinx, Inc. | Methods and circuits for preventing the overwriting of memory frames in programmable logic devices |
US6996713B1 (en) | 2002-03-29 | 2006-02-07 | Xilinx, Inc. | Method and apparatus for protecting proprietary decryption keys for programmable logic devices |
EP1600883A3 (en) * | 2004-05-28 | 2009-04-01 | Panasonic Electric Works Co., Ltd. | Object recognition system |
EP1600883A2 (en) | 2004-05-28 | 2005-11-30 | Matsushita Electric Works, Ltd. | Object recognition system |
US20060136110A1 (en) * | 2004-12-20 | 2006-06-22 | Caterpillar Inc. | Adaptive vibration management system for a work machine |
US7206681B2 (en) | 2004-12-20 | 2007-04-17 | Caterpillar Inc. | Adaptive vibration management system for a work machine |
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