DE59906216D1 - METHOD FOR THE VERTICAL INTEGRATION OF ACTIVE SWITCHING LEVELS - Google Patents

METHOD FOR THE VERTICAL INTEGRATION OF ACTIVE SWITCHING LEVELS

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Publication number
DE59906216D1
DE59906216D1 DE59906216T DE59906216T DE59906216D1 DE 59906216 D1 DE59906216 D1 DE 59906216D1 DE 59906216 T DE59906216 T DE 59906216T DE 59906216 T DE59906216 T DE 59906216T DE 59906216 D1 DE59906216 D1 DE 59906216D1
Authority
DE
Germany
Prior art keywords
substrate
areas
connecting areas
integrated circuit
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE59906216T
Other languages
German (de)
Inventor
Michael Feil
Christof Landesberger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
S Aqua Semiconductor LLC
Original Assignee
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Application granted granted Critical
Publication of DE59906216D1 publication Critical patent/DE59906216D1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01061—Promethium [Pm]
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    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Processing Of Color Television Signals (AREA)

Abstract

In a method for vertically integrating active circuit planes, a first substrate having at least one integrated circuit in a first main surface thereof and further having connecting areas for the integrated circuit as well as outer connecting areas on the first main surface is provided in a first step. A second substrate having at least one integrated circuit in a first main surface thereof and further having connecting areas for the integrated circuit as well as open or openable areas on the first main surface is provided. The first main surfaces of the first and second substrates are joined in such a way that the connecting areas of the first substrate are connected to those of the second substrate in an electrically conductive manner in such a way that the outer connecting areas of the first substrate are in alignment with the open or openable areas of the second substrate. Subsequently, the second substrate is thinned and the outer connecting areas are exposed through the open or openable areas. The resultant chips can be further processed making use of standard methods.
DE59906216T 1998-12-08 1999-12-06 METHOD FOR THE VERTICAL INTEGRATION OF ACTIVE SWITCHING LEVELS Expired - Lifetime DE59906216D1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19856573A DE19856573C1 (en) 1998-12-08 1998-12-08 Vertical integration of active circuit planes involves connecting two substrates so connection surfaces are electrically connected, reducing second substrate, freeing external connection surfaces
PCT/EP1999/009540 WO2000035007A1 (en) 1998-12-08 1999-12-06 Method for vertically integrating active circuit planes and vertically integrated circuit produced using said method

Publications (1)

Publication Number Publication Date
DE59906216D1 true DE59906216D1 (en) 2003-08-07

Family

ID=7890375

Family Applications (2)

Application Number Title Priority Date Filing Date
DE19856573A Expired - Fee Related DE19856573C1 (en) 1998-12-08 1998-12-08 Vertical integration of active circuit planes involves connecting two substrates so connection surfaces are electrically connected, reducing second substrate, freeing external connection surfaces
DE59906216T Expired - Lifetime DE59906216D1 (en) 1998-12-08 1999-12-06 METHOD FOR THE VERTICAL INTEGRATION OF ACTIVE SWITCHING LEVELS

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE19856573A Expired - Fee Related DE19856573C1 (en) 1998-12-08 1998-12-08 Vertical integration of active circuit planes involves connecting two substrates so connection surfaces are electrically connected, reducing second substrate, freeing external connection surfaces

Country Status (5)

Country Link
US (1) US6444493B1 (en)
EP (1) EP1151472B1 (en)
AT (1) ATE244455T1 (en)
DE (2) DE19856573C1 (en)
WO (1) WO2000035007A1 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
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DE19918671B4 (en) * 1999-04-23 2006-03-02 Giesecke & Devrient Gmbh Vertically integrable circuit and method for its manufacture
AU2001286711A1 (en) * 2000-09-13 2002-03-26 Applied Materials, Inc. Micromachined silicon block vias for transferring electrical signals to the backside of a silicon wafer
DE10131011B4 (en) * 2001-06-27 2016-02-18 Infineon Technologies Ag Semiconductor chip and arrangement of a semiconductor device on a substrate
DE10222959B4 (en) * 2002-05-23 2007-12-13 Schott Ag Micro-electromechanical component and method for the production of micro-electromechanical components
JP3910493B2 (en) * 2002-06-14 2007-04-25 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
US20040124538A1 (en) * 2002-12-31 2004-07-01 Rafael Reif Multi-layer integrated semiconductor structure
US7064055B2 (en) * 2002-12-31 2006-06-20 Massachusetts Institute Of Technology Method of forming a multi-layer semiconductor structure having a seamless bonding interface
US7067909B2 (en) * 2002-12-31 2006-06-27 Massachusetts Institute Of Technology Multi-layer integrated semiconductor structure having an electrical shielding portion
DE10342980B3 (en) 2003-09-17 2005-01-05 Disco Hi-Tec Europe Gmbh Semiconductor chip stack formation method for manufacture of 3D-packages with function testing of chips for removal or unacceptable chips and replacement by acceptable chips
DE102004014214B3 (en) * 2004-03-23 2005-09-15 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Gluing system for fastening transponder chip to substrate uses thick layer of electrically conducting glue with matrix loaded with conducting particles forming bridges between electrodes
JP5169985B2 (en) * 2009-05-12 2013-03-27 富士ゼロックス株式会社 Semiconductor device
DE102011116409B3 (en) 2011-10-19 2013-03-07 Austriamicrosystems Ag Method for producing thin semiconductor components
US10438838B2 (en) 2016-09-01 2019-10-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and related method

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US5071792A (en) 1990-11-05 1991-12-10 Harris Corporation Process for forming extremely thin integrated circuit dice
US5202754A (en) 1991-09-13 1993-04-13 International Business Machines Corporation Three-dimensional multichip packages and methods of fabrication
US5266511A (en) * 1991-10-02 1993-11-30 Fujitsu Limited Process for manufacturing three dimensional IC's
DE4238137A1 (en) * 1992-11-12 1994-05-19 Ant Nachrichtentech Hybrid semiconductor structure mfg. system - with semiconductor chips incorporating semiconductor components attached to semiconductor carrier substrate
WO1995009438A1 (en) 1993-09-30 1995-04-06 Kopin Corporation Three-dimensional processor using transferred thin film circuits
US5880010A (en) * 1994-07-12 1999-03-09 Sun Microsystems, Inc. Ultrathin electronics
DE4427515C1 (en) * 1994-08-03 1995-08-24 Siemens Ag Production of three=dimensional solid state circuit
MY114888A (en) 1994-08-22 2003-02-28 Ibm Method for forming a monolithic electronic module by stacking planar arrays of integrated circuit chips
DE4433833A1 (en) 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Method for producing a three-dimensional integrated circuit while achieving high system yields
DE4433845A1 (en) 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Method of manufacturing a three-dimensional integrated circuit
DE4433846C2 (en) 1994-09-22 1999-06-02 Fraunhofer Ges Forschung Method of making a vertical integrated circuit structure
DE19516487C1 (en) * 1995-05-05 1996-07-25 Fraunhofer Ges Forschung Vertical integration process for microelectronic system
KR100522223B1 (en) * 1997-01-24 2005-12-21 로무 가부시키가이샤 Semiconductor device and method for manufacturing thereof
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US6153495A (en) * 1998-03-09 2000-11-28 Intersil Corporation Advanced methods for making semiconductor devices by low temperature direct bonding
US6287940B1 (en) * 1999-08-02 2001-09-11 Honeywell International Inc. Dual wafer attachment process

Also Published As

Publication number Publication date
WO2000035007A1 (en) 2000-06-15
EP1151472A1 (en) 2001-11-07
DE19856573C1 (en) 2000-05-18
EP1151472B1 (en) 2003-07-02
ATE244455T1 (en) 2003-07-15
US6444493B1 (en) 2002-09-03

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Owner name: IP BEWERTUNGS AG (IPB), 20354 HAMBURG, DE

8327 Change in the person/name/address of the patent owner

Owner name: IP VERWERTUNGS GMBH, 82031 GRUENWALD, DE

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Owner name: TPL THREE LLC,, WILMINGTON, DEL., US

8328 Change in the person/name/address of the agent

Representative=s name: DENDORFER & HERRMANN PATENTANWAELTE PARTNERSCHAFT,