DE50114463D1 - Integrated circuit with test mode and method for testing a plurality of such integrated circuits - Google Patents

Integrated circuit with test mode and method for testing a plurality of such integrated circuits

Info

Publication number
DE50114463D1
DE50114463D1 DE50114463T DE50114463T DE50114463D1 DE 50114463 D1 DE50114463 D1 DE 50114463D1 DE 50114463 T DE50114463 T DE 50114463T DE 50114463 T DE50114463 T DE 50114463T DE 50114463 D1 DE50114463 D1 DE 50114463D1
Authority
DE
Germany
Prior art keywords
testing
test mode
integrated circuit
integrated circuits
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE50114463T
Other languages
German (de)
Inventor
Stefan Dr Dietrich
Patrick Heyne
Thilo Marx
Sabine Schoeniger
Michael Sommer
Thomas Hein
Michael Markert
Torsten Partsch
Peter Schroegmeier
Christian Weis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE50114463D1 publication Critical patent/DE50114463D1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/003—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation in serial memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
DE50114463T 2000-10-20 2001-09-24 Integrated circuit with test mode and method for testing a plurality of such integrated circuits Expired - Lifetime DE50114463D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10052211A DE10052211A1 (en) 2000-10-20 2000-10-20 Test arrangement for integrated circuit memory chips

Publications (1)

Publication Number Publication Date
DE50114463D1 true DE50114463D1 (en) 2008-12-18

Family

ID=7660546

Family Applications (2)

Application Number Title Priority Date Filing Date
DE10052211A Withdrawn DE10052211A1 (en) 2000-10-20 2000-10-20 Test arrangement for integrated circuit memory chips
DE50114463T Expired - Lifetime DE50114463D1 (en) 2000-10-20 2001-09-24 Integrated circuit with test mode and method for testing a plurality of such integrated circuits

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE10052211A Withdrawn DE10052211A1 (en) 2000-10-20 2000-10-20 Test arrangement for integrated circuit memory chips

Country Status (6)

Country Link
US (1) US6670802B2 (en)
EP (1) EP1205938B1 (en)
JP (1) JP3588075B2 (en)
KR (1) KR100444788B1 (en)
DE (2) DE10052211A1 (en)
TW (1) TW523597B (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003019720A1 (en) * 2001-08-23 2003-03-06 Ems Technologies, Inc. Microstrip phase shifter
US6809914B2 (en) 2002-05-13 2004-10-26 Infineon Technologies Ag Use of DQ pins on a ram memory chip for a temperature sensing protocol
US6873509B2 (en) 2002-05-13 2005-03-29 Infineon Technologies Ag Use of an on-die temperature sensing scheme for thermal protection of DRAMS
US6711091B1 (en) 2002-09-27 2004-03-23 Infineon Technologies Ag Indication of the system operation frequency to a DRAM during power-up
US6985400B2 (en) * 2002-09-30 2006-01-10 Infineon Technologies Ag On-die detection of the system operation frequency in a DRAM to adjust DRAM operations
DE10338030B3 (en) * 2003-08-19 2005-04-28 Infineon Technologies Ag Integrated circuit for testing circuit components of a semiconductor chip
KR100641706B1 (en) * 2004-11-03 2006-11-03 주식회사 하이닉스반도체 On-chip self test circuit and self test method of signal distortion
US20070088993A1 (en) * 2005-10-18 2007-04-19 Ronald Baker Memory tester having master/slave configuration
US20070109888A1 (en) * 2005-11-14 2007-05-17 Ronald Baker Integrated circuit with test circuit
US8977912B2 (en) * 2007-05-07 2015-03-10 Macronix International Co., Ltd. Method and apparatus for repairing memory
US7554858B2 (en) * 2007-08-10 2009-06-30 Micron Technology, Inc. System and method for reducing pin-count of memory devices, and memory device testers for same
US7916575B2 (en) * 2008-12-23 2011-03-29 Emanuele Confalonieri Configurable latching for asynchronous memories
US10197442B2 (en) * 2015-06-01 2019-02-05 Arizona Board Of Regents On Behalf Of The University Of Arizona Dual-comb spectroscopy with a free-running bidirectionally mode-locked fiber laser
CN108762407B (en) * 2018-04-28 2020-05-15 华勤通讯技术有限公司 Circuit board assembly, board card and electronic equipment

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4490783A (en) * 1981-07-02 1984-12-25 Texas Instruments Incorporated Microcomputer with self-test of microcode
US4594711A (en) * 1983-11-10 1986-06-10 Texas Instruments Incorporated Universal testing circuit and method
US4672610A (en) * 1985-05-13 1987-06-09 Motorola, Inc. Built in self test input generator for programmable logic arrays
JPH081760B2 (en) * 1987-11-17 1996-01-10 三菱電機株式会社 Semiconductor memory device
JPH01196158A (en) * 1988-01-31 1989-08-07 Nec Corp Semiconductor integrated circuit
US4893311A (en) * 1988-04-25 1990-01-09 Motorola, Inc. CMOS implementation of a built-in self test input generator (BISTIG)
JPH02206773A (en) * 1989-02-06 1990-08-16 Mitsubishi Electric Corp Test circuit for semiconductor integrated circuit
US5361264A (en) * 1989-07-03 1994-11-01 Raytheon Company Mode programmable VLSI data registers
JPH03252574A (en) * 1990-03-01 1991-11-11 Sharp Corp Semiconductor integrated circuit
US5301156A (en) * 1991-07-18 1994-04-05 Hewlett-Packard Company Configurable self-test for embedded RAMs
US5546406A (en) * 1992-06-29 1996-08-13 Tandem Computers, Inc. Cell architecture for built-in self-test of application specific integrated circuits
JP3080847B2 (en) * 1994-10-05 2000-08-28 日本電気株式会社 Semiconductor storage device
KR0172347B1 (en) * 1995-12-23 1999-03-30 김광호 Parallel test circuit of semiconductor memory equipment
JPH1172538A (en) 1997-08-29 1999-03-16 Ando Electric Co Ltd Ic testing device, measurement method and storage medium for ic testing device
JPH11219600A (en) * 1998-02-03 1999-08-10 Mitsubishi Electric Corp Semiconductor integrated circuit device
KR100301044B1 (en) * 1998-08-13 2001-09-06 윤종용 Semiconductor device able to control internal signal & testing method

Also Published As

Publication number Publication date
KR100444788B1 (en) 2004-08-21
EP1205938A2 (en) 2002-05-15
EP1205938A3 (en) 2005-04-20
US6670802B2 (en) 2003-12-30
JP3588075B2 (en) 2004-11-10
EP1205938B1 (en) 2008-11-05
KR20020031035A (en) 2002-04-26
JP2002221555A (en) 2002-08-09
TW523597B (en) 2003-03-11
US20020133750A1 (en) 2002-09-19
DE10052211A1 (en) 2002-05-08

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

8364 No opposition during term of opposition