DE59801360D1 - TEST CIRCUIT AND METHOD FOR TESTING A DIGITAL SEMICONDUCTOR CIRCUIT ARRANGEMENT - Google Patents

TEST CIRCUIT AND METHOD FOR TESTING A DIGITAL SEMICONDUCTOR CIRCUIT ARRANGEMENT

Info

Publication number
DE59801360D1
DE59801360D1 DE59801360T DE59801360T DE59801360D1 DE 59801360 D1 DE59801360 D1 DE 59801360D1 DE 59801360 T DE59801360 T DE 59801360T DE 59801360 T DE59801360 T DE 59801360T DE 59801360 D1 DE59801360 D1 DE 59801360D1
Authority
DE
Germany
Prior art keywords
testing
digital semiconductor
circuit arrangement
test circuit
semiconductor circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE59801360T
Other languages
German (de)
Inventor
Dominique Savignac
Wolfgang Nikutta
Michael Kund
Broeke Jan Ten
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE59801360D1 publication Critical patent/DE59801360D1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
DE59801360T 1998-02-17 1998-09-30 TEST CIRCUIT AND METHOD FOR TESTING A DIGITAL SEMICONDUCTOR CIRCUIT ARRANGEMENT Expired - Lifetime DE59801360D1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19806455 1998-02-17
PCT/DE1998/002895 WO1999043004A1 (en) 1998-02-17 1998-09-30 Circuit and method for testing a digital semi-conductor circuit

Publications (1)

Publication Number Publication Date
DE59801360D1 true DE59801360D1 (en) 2001-10-04

Family

ID=7857962

Family Applications (1)

Application Number Title Priority Date Filing Date
DE59801360T Expired - Lifetime DE59801360D1 (en) 1998-02-17 1998-09-30 TEST CIRCUIT AND METHOD FOR TESTING A DIGITAL SEMICONDUCTOR CIRCUIT ARRANGEMENT

Country Status (8)

Country Link
US (1) US6256243B1 (en)
EP (1) EP1055238B1 (en)
JP (1) JP3842971B2 (en)
KR (1) KR100383479B1 (en)
CN (1) CN1133173C (en)
DE (1) DE59801360D1 (en)
TW (1) TW407209B (en)
WO (1) WO1999043004A1 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1369878A1 (en) * 2002-06-04 2003-12-10 Infineon Technologies AG System for testing a group of functionally independent memories and for replacing failing memory words
DE10226585C1 (en) * 2002-06-14 2003-12-11 Infineon Technologies Ag Random-access memory circuit with in-built testing aid for rapid parallel testing of all memory banks
US7073100B2 (en) * 2002-11-11 2006-07-04 International Business Machines Corporation Method for testing embedded DRAM arrays
JP4400081B2 (en) 2003-04-08 2010-01-20 エルピーダメモリ株式会社 Semiconductor memory device
US6999887B2 (en) * 2003-08-06 2006-02-14 Infineon Technologies Ag Memory cell signal window testing apparatus
KR100558492B1 (en) * 2003-11-14 2006-03-07 삼성전자주식회사 Semiconductor memory device and test pattern data generating method thereof
KR100640635B1 (en) 2005-02-07 2006-10-31 삼성전자주식회사 Semiconductor memory device with various test data pattern
TWI425517B (en) * 2009-04-21 2014-02-01 Etron Technology Inc Testing system and method thereof
KR101192556B1 (en) * 2010-08-12 2012-10-17 한국항공우주산업 주식회사 Method for design verification system of digital circuits and the verification system thereof
JP5740296B2 (en) 2011-12-16 2015-06-24 株式会社東芝 Semiconductor memory device, semiconductor memory device control method, and control program
CN104237771B (en) * 2013-06-20 2017-08-25 京微雅格（北京）科技有限公司 The error-detecting method and circuit of a kind of fpga chip
WO2020042906A1 (en) * 2018-08-31 2020-03-05 Changxin Memory Technologies, Inc. Test methods, tester, load board and test system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0419899A (en) * 1990-05-11 1992-01-23 Mitsubishi Electric Corp Test device for semiconductor memory
KR950000305Y1 (en) * 1991-12-23 1995-01-16 금성일렉트론 주식회사 Test mode circuit of memory device
EP0632468A1 (en) * 1993-06-30 1995-01-04 International Business Machines Corporation Fast data compression circuit for semiconductor memory chips including an abist structure
US5490115A (en) * 1994-07-29 1996-02-06 Cypress Semiconductor Corp. Method and apparatus for writing to memory cells in a minimum number of cycles during a memory test operation
JPH0963297A (en) * 1995-08-29 1997-03-07 Mitsubishi Electric Corp Semiconductor memory
US5661690A (en) * 1996-02-27 1997-08-26 Micron Quantum Devices, Inc. Circuit and method for performing tests on memory array cells using external sense amplifier reference current

Also Published As

Publication number Publication date
EP1055238A1 (en) 2000-11-29
CN1285073A (en) 2001-02-21
TW407209B (en) 2000-10-01
KR100383479B1 (en) 2003-05-12
JP3842971B2 (en) 2006-11-08
EP1055238B1 (en) 2001-08-29
WO1999043004A1 (en) 1999-08-26
US6256243B1 (en) 2001-07-03
KR20010040999A (en) 2001-05-15
CN1133173C (en) 2003-12-31
JP2002504736A (en) 2002-02-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE