DE4429289A1 - Integrated circuit for e.g. suppressing high frequency interference signal - Google Patents

Integrated circuit for e.g. suppressing high frequency interference signal

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Publication number
DE4429289A1
DE4429289A1 DE4429289A DE4429289A DE4429289A1 DE 4429289 A1 DE4429289 A1 DE 4429289A1 DE 4429289 A DE4429289 A DE 4429289A DE 4429289 A DE4429289 A DE 4429289A DE 4429289 A1 DE4429289 A1 DE 4429289A1
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Germany
Prior art keywords
capacitors
semiconductor chip
electrode
circuit arrangement
connection
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DE4429289A
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German (de)
Inventor
Hans-Eberhard Dipl Ing Kroebel
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Conti Temic Microelectronic GmbH
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Temic Telefunken Microelectronic GmbH
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Priority to DE4429289A priority Critical patent/DE4429289A1/en
Publication of DE4429289A1 publication Critical patent/DE4429289A1/en
Withdrawn legal-status Critical Current

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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
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    • H01L2224/4805—Shape
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The circuit includes at least a substrate support formed of two capacitors (2,2'), and a semiconductor chip (1). A dielectric (22) is sandwiched by electrodes (20,21,21') and is present in both capacitors. Each electrode is coupled to a terminal of the semiconductor chip. Pref. one chip terminal forms a substrate terminal (11). The substrate terminal is coupled to the upper capacitor electrode (20) via a solder (4) or a conductive adhesive. This upper electrode is pref. coupled to a reference potential terminal (M) of the integrated circuit. The electrodes and dielectric may be folded in a meander.

Description

Die Erfindung betrifft eine integrierte Schaltungsan­ ordnung (IC) nach dem Oberbegriff des Anspruchs 1. Bei derartigen Schaltungsanordnungen werden die zur Unter­ drückung von hochfrequenten Störsignalen oder zur Rea­ lisierung großer Zeitkonstanten erforderlichen Konden­ satoren aufgrund der benötigten Kapazitätswerte als ex­ terne, d. h. außerhalb des ICs angeordnete Kondensato­ ren ausgebildet.The invention relates to an integrated circuit order (IC) according to the preamble of claim 1. bei such circuits become the sub pressing of high-frequency interference signals or for rea large time constants required due to the required capacity values as ex terne, d. H. Condensate located outside the IC ren trained.

Externe Kondensatoren stellen für viele Anwendungen aufgrund der zusätzlich beanspruchten Platinenfläche und des zusätzlichen Arbeitsaufwandes bei deren Montage einen erheblichen Kostenfaktor dar. Zudem sind Schaltungsanordnungen mit externen Kondensatoren nicht zur Realisierung von Hochfrequenzschaltungen geeignet, da die für diesen Anwendungsfall langen Leitungen vom Halbleiterchip des ICs zum externen Kondensator als mögliche Störsenken oder Störquellen anzusehen sind.External capacitors make for many applications due to the additional stress on the board area and the additional work involved in their assembly represent a significant cost factor Circuit arrangements with external capacitors are not suitable for realizing high-frequency circuits, since the long lines for this application from Semiconductor chip of the IC to the external capacitor as possible interference sinks or sources of interference are to be considered.

Der Erfindung liegt die Aufgabe zugrunde, eine Schaltungsanordnung gemäß dem Oberbegriff des Anspruch 1 anzugeben, die kostengünstig und einfach herzustellen ist und die auch mit Hochfrequenzsignalen zuverlässig betrieben werden kann.The invention has for its object a Circuit arrangement according to the preamble of the claim 1 specify that inexpensive and easy to manufacture is reliable and also with high-frequency signals can be operated.

Diese Aufgabe wird erfindungsgemäß durch die Merkmale im Kennzeichen des Patentanspruchs 1 gelöst. Vorteil­ hafte Ausgestaltungen und Weiterbildungen ergeben sich aus den Unteransprüchen.This object is achieved by the features solved in the characterizing part of claim 1. Advantage  there are tough refinements and developments from the subclaims.

Die erfindungsgemäße integrierte Schaltungsanordnung weist einen Substratträger auf, der als mindestens ein Kondensator mit zwei durch ein Dielektrikum voneinander getrennten Elektroden ausgebildet ist. Auf dem Sub­ stratträger ist mindestens ein Halbleiterchip ange­ bracht. Der Halbleiterchip weist mindestens zwei mit jeweils einer der Elektroden des Kondensators verbun­ dene Anschlüsse auf. Der mit der ersten Elektrode des Kondensators verbundene erste Anschluß des Halbleiter­ chips ist vorzugsweise als ein am Substrat des Halblei­ terchips angeordneter Substratanschluß ausgebildet. Die erste Elektrode des Kondensators und der Substratan­ schluß des Halbleiterchips sind vorzugsweise über ein Lot oder einen elektrisch leitenden Kleber miteinander verbunden. Eine derartige Verbindung dient neben der elektrischen Kontaktierung auch zur mechanischen Befe­ stigung des Halbleiterchips auf dem Substratträger. Der ersten Elektrode des Kondensators wird vorzugsweise ein Bezugspotential zugeführt. Die zweite Elektrode des Kondensators ist mit dem zweiten Anschluß des Halblei­ terchips, vorzugsweise einem Anschluß, an dem hochfre­ quente Störsignale auftreten, verbunden. Auf diese Wei­ se ist der Kondensator auf kürzestem Weg und folglich induktivitätsarm mit dem Halbleiterchip verbunden. Um die Kapazität des Kondensators zu vergrößern, weisen dessen Elektroden und das Dielektrikum vorzugsweise mä­ anderförmige Struktur auf.The integrated circuit arrangement according to the invention has a substrate support that is considered at least one Capacitor with two through a dielectric from each other separate electrodes is formed. On the sub The carrier is at least one semiconductor chip brings. The semiconductor chip has at least two one of the electrodes of the capacitor is connected connections. The one with the first electrode of the Capacitor connected first terminal of the semiconductor Chips is preferably as one on the substrate of the semi-lead terchips arranged substrate connection formed. The first electrode of the capacitor and the substrate circuit of the semiconductor chip are preferably a Solder or an electrically conductive glue together connected. Such a connection serves in addition to electrical contacting also for mechanical fixation Stigation of the semiconductor chip on the substrate carrier. Of the first electrode of the capacitor is preferably a Reference potential supplied. The second electrode of the The capacitor is connected to the second connection of the half lead terchips, preferably a connector on the hochfre quent interference signals occur, connected. In this way se is the capacitor on the shortest path and consequently low inductance connected to the semiconductor chip. Around to increase the capacitance of the capacitor whose electrodes and the dielectric are preferably mä other structure.

Durch Strukturierung der auf dem Dielektrikum aufge­ brachten Elektroden ist ein Substratträger mit mehreren Kondensatoren herstellbar. Diese Kondensatoren weisen vorzugsweise eine gemeinsame erste Elektrode auf, die vorzugsweise mit dem Substratanschluß des Halbleiter­ chips verbunden ist. Die durch das Dielektrikum von der ersten Elektrode beabstandeten zweiten Elektroden der Kondensatoren sind mit jeweils einem weiteren Anschluß des Halbleiterchips verbunden. Mit einem derartigen Substratträger lassen sich hochfrequente Störsignale an mehreren Anschlüsse eines oder mehrerer Halbleiterchips gegen ein gemeinsames Bezugspotential ableiten.By structuring the on the dielectric brought electrodes is a substrate carrier with several Capacitors can be manufactured. These capacitors have preferably a common first electrode on the preferably with the substrate connection of the semiconductor chips is connected. The through the dielectric of the  first electrode spaced apart second electrodes Capacitors are each with an additional connection of the semiconductor chip connected. With such a Substrate carriers can be subjected to high-frequency interference signals multiple connections of one or more semiconductor chips derive against a common reference potential.

Anwendungsschaltungen, zu deren Realisierung Konden­ satoren benötigt werden, sind mit dem erfindungsgemäßen IC kostengünstig, einfach und platzsparend herstellbar, da zu deren Herstellung keine externen Kondensatoren benötigt werden und da die benötigten Kondensatoren gleichzeitig den zur Herstellung des ICs erforderlichen Substratträger bilden. Aufgrund der kurzen und folglich induktivitätsarmen Leitungen vom Halbleiterchip zu den Kondensatoren sind die Kondensatoren insbesondere zur Unterdrückung von an Anschlüssen der Schaltungsanord­ nung anstehenden hochfrequenten Störsignalen, bei­ spielsweise zur Unterdrückung von Störspannungen an Versorgungsanschlüssen des Halbleiterchips, bestens ge­ eignet. Die Kondensatoren eignen sich insbesondere zur Unterdrückung von im Halbleiterchip selbst erzeugten hochfrequenten Störsignalen. Auf diese Art werden die elektrischen Eigenschaften des ICs, beispielsweise die Störempfindlichkeit und der Signalrauschabstand, ver­ bessert.Application circuits, for the implementation of which are needed are with the invention IC inexpensive, simple and space-saving to manufacture, because there are no external capacitors to manufacture them and the capacitors needed at the same time that required to manufacture the IC Form substrate carrier. Because of the short and consequently Low inductance lines from the semiconductor chip to the Capacitors are the capacitors in particular Suppression of connections of the circuit arrangement pending high-frequency interference signals for example to suppress interference voltages Supply connections of the semiconductor chip, ideally ge is suitable. The capacitors are particularly suitable for Suppression of self-generated in the semiconductor chip high-frequency interference signals. In this way, the electrical properties of the IC, for example the Noise sensitivity and signal-to-noise ratio, ver improves.

Die Erfindung wird anhand der Figur im folgenden näher beschrieben. Die Figur zeigt den aus zwei Kondensatoren 2, 2′ mit einer gemeinsamen ersten Elektrode 20, mit zwei zweiten Elektroden 21, 21 ′ und einem gemeinsamen Dielektrikum 22 gebildeten Substratträger. Die mit dem Bezugspotentialanschluß M des ICs verbundene erste Elektrode 20 der Kondensatoren 2, 2′ ist über ein Lot 4 mit dem Substratanschluß 11, beispielsweise dem Masse­ anschluß des Halbleiterchips 1, verbunden. Der Anschluß 10, beispielsweise ein erster Versorgungsanschluß des Halbleiterchips 1, ist über den Bonddraht 3 auf kürze­ stem Weg mit der am Anschluß VCC des ICs angeschlosse­ nen zweiten Elektrode 21 des Kondensators 2 verbunden. Der Bonddraht 3 wird hierzu an der als Ausnehmung aus­ geführten Durchkontaktierstelle 23 durch die erste Elektrode 20 und durch das Dielektrikum 22 hindurch mit der zweiten Elektrode 2.1 verbunden. Der Anschluß 10′ beispielsweise ein zweiter Versorgungsanschluß des Halbleiterchips 1, ist über den Bonddraht 3′ und über die Durchkontaktierstelle 23′ mit der am Anschluß VCCA des ICs angeschlossenen zweiten Elektrode 21′ des zweiten Kondensators 2′ verbunden. Die Kondensatoren 2, 2′ dienen im vorliegenden Beispiel zur Unterdrückung von hochfrequenten im Halbleiterchip 1 selbst erzeugten Störsignalen, die, falls sie nicht unterdrückt werden, am Bezugspotentialanschluß M oder an den Anschlüssen VCC, VCCA des ICs als steile, nadelförmige Störspan­ nungsspitzen nachweisbar sind.The invention is described in more detail below with reference to the figure. The figure shows the substrate carrier formed from two capacitors 2 , 2 'with a common first electrode 20 , with two second electrodes 21 , 21 ' and a common dielectric 22 . The first electrode 20 of the capacitors 2 , 2 'connected to the reference potential connection M of the IC is connected via a solder 4 to the substrate connection 11 , for example the ground connection of the semiconductor chip 1 . The connection 10 , for example a first supply connection of the semiconductor chip 1 , is connected via the bonding wire 3 in a short way to the second electrode 21 of the capacitor 2 which is connected to the connection V CC of the IC. For this purpose, the bonding wire 3 is connected at the via 23, which is designed as a recess, through the first electrode 20 and through the dielectric 22 to the second electrode 2.1 . The connection 10 ', for example a second supply connection of the semiconductor chip 1 , is connected via the bonding wire 3 ' and via the via 23 'to the second electrode 21 ' of the second capacitor 2 'connected to the connection V CCA of the IC. The capacitors 2 , 2 'are used in the present example to suppress high-frequency interference signals generated in the semiconductor chip 1 itself, which, if they are not suppressed, at the reference potential connection M or at the connections V CC , V CCA of the IC as steep, needle-shaped interference voltage peaks detectable are.

Claims (7)

1. Integrierte Schaltungsanordnung (IC) mit mindestens einem auf einem Substratträger angebrachten Halbleiter­ chip (1), dadurch gekennzeichnet, daß zumindest ein Teil des Substratträgers als mindestens ein Kondensator (2, 2′) ausgebildet ist, daß jeder Kondensator (2, 2′) zwei durch ein Dielektrikum (22) voneinander beabstan­ dete Elektroden (20, 21, 21′) aufweist, und daß jede Elektrode mit jeweils einem Anschluß des Halbleiter­ chips (1) verbunden ist.1. Integrated circuit arrangement (IC) with at least one semiconductor chip attached to a substrate carrier ( 1 ), characterized in that at least part of the substrate carrier is designed as at least one capacitor ( 2 , 2 ') that each capacitor ( 2 , 2 ' ) two through a dielectric ( 22 ) apart from each other electrodes ( 20 , 21 , 21 '), and that each electrode is connected to one connection of the semiconductor chip ( 1 ). 2. Schaltungsanordnung nach Anspruch 1, dadurch gekenn­ zeichnet, daß ein Anschluß des Halbleiterchips (1) als Substratanschluß (11) ausgeführt ist, der über ein Lot (4) oder einen elektrisch leitenden Kleber mit der ersten Elektrode (20) zumindest eines der Kondensatoren (2, 2′) verbunden ist.2. Circuit arrangement according to claim 1, characterized in that a connection of the semiconductor chip ( 1 ) is designed as a substrate connection ( 11 ), which via a solder ( 4 ) or an electrically conductive adhesive with the first electrode ( 20 ) at least one of the capacitors ( 2 , 2 ') is connected. 3. Schaltungsanordnung nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß die erste Elektrode (20) zumindest eines der Kondensatoren (2, 2′) mit einem Bezugspo­ tentialanschluß (M) des ICs verbunden ist.3. Circuit arrangement according to claim 1 or 2, characterized in that the first electrode ( 20 ) at least one of the capacitors ( 2 , 2 ') is connected to a reference potential connection (M) of the IC. 4. Schaltungsanordnung nach einem der vorherigen An­ sprüche, dadurch gekennzeichnet, daß die Elektroden (20, 21, 21′) und das Dielektrikum (22) zumindest eines der Kondensatoren (2, 2′) eine mäanderförmig gefaltete Struktur aufweisen.4. Circuit arrangement according to one of the preceding claims, characterized in that the electrodes ( 20 , 21 , 21 ') and the dielectric ( 22 ) at least one of the capacitors ( 2 , 2 ') have a meandering folded structure. 5. Schaltungsanordnung nach einem der vorherigen An­ sprüche, dadurch gekennzeichnet, daß zumindest zwei Kondensatoren (2, 2′) eine gemeinsame erste Elektrode (20) und ein gemeinsames Dielektrikum (22) aufweisen.5. Circuit arrangement according to one of the preceding claims, characterized in that at least two capacitors ( 2 , 2 ') have a common first electrode ( 20 ) and a common dielectric ( 22 ). 6. Verwendung einer Schaltungsanordnung nach einem der vorherigen Ansprüche zur Unterdrückung von an minde­ stens einem Anschluß (VCC, VCCA) der Schaltungsanord­ nung anstehenden hochfrequenten Störsignalen.6. Use of a circuit arrangement according to one of the preceding claims for suppressing at least one connection (V CC , V CCA ) of the circuit arrangement pending high-frequency interference signals. 7. Verwendung einer Schaltungsanordnung nach Anspruch 6 zur Unterdrückung von im Halbleiterchip (1) selbst er­ zeugten hochfrequenten Störsignalen.7. Use of a circuit arrangement according to claim 6 for suppressing in the semiconductor chip ( 1 ) itself it generated high-frequency interference signals.
DE4429289A 1994-08-18 1994-08-18 Integrated circuit for e.g. suppressing high frequency interference signal Withdrawn DE4429289A1 (en)

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Publication number Priority date Publication date Assignee Title
EP0978854A2 (en) * 1998-08-04 2000-02-09 Kabushiki Kaisha Toshiba Ceramic capacitor mounting structure
EP1104026A2 (en) * 1999-11-26 2001-05-30 Nokia Mobile Phones Ltd. Ground plane for a semiconductor chip

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DE3134680A1 (en) * 1980-09-02 1982-04-08 Thomson-CSF, 75360 Paris Ceramic micro-encapsulation housing for electronic circuits
US4638400A (en) * 1985-10-24 1987-01-20 General Electric Company Refractory metal capacitor structures, particularly for analog integrated circuit devices
DD250004A1 (en) * 1986-06-11 1987-09-23 Robotron Rationalisierung CONDENSER, IN PARTICULAR FOR BLOCKING THE OPERATING VOLTAGE FOR MONOLITHIC CIRCUITS
DE3900512A1 (en) * 1989-01-10 1990-07-19 Tucker Gmbh Bostik Semiconductor component for a switched-mode power supply
EP0563873A2 (en) * 1992-04-03 1993-10-06 Matsushita Electric Industrial Co., Ltd. High frequency ceramic multi-layer substrate
EP0596596A1 (en) * 1992-08-31 1994-05-11 Hewlett-Packard Company Mounting for a high frequency integrated circuit
DE4219031C2 (en) * 1992-06-10 1994-11-10 Siemens Ag Multi-chip module with capacitor, which is realized on the carrier made of silicon (monocrystalline substrate)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3134680A1 (en) * 1980-09-02 1982-04-08 Thomson-CSF, 75360 Paris Ceramic micro-encapsulation housing for electronic circuits
US4638400A (en) * 1985-10-24 1987-01-20 General Electric Company Refractory metal capacitor structures, particularly for analog integrated circuit devices
DD250004A1 (en) * 1986-06-11 1987-09-23 Robotron Rationalisierung CONDENSER, IN PARTICULAR FOR BLOCKING THE OPERATING VOLTAGE FOR MONOLITHIC CIRCUITS
DE3900512A1 (en) * 1989-01-10 1990-07-19 Tucker Gmbh Bostik Semiconductor component for a switched-mode power supply
EP0563873A2 (en) * 1992-04-03 1993-10-06 Matsushita Electric Industrial Co., Ltd. High frequency ceramic multi-layer substrate
DE4219031C2 (en) * 1992-06-10 1994-11-10 Siemens Ag Multi-chip module with capacitor, which is realized on the carrier made of silicon (monocrystalline substrate)
EP0596596A1 (en) * 1992-08-31 1994-05-11 Hewlett-Packard Company Mounting for a high frequency integrated circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0978854A2 (en) * 1998-08-04 2000-02-09 Kabushiki Kaisha Toshiba Ceramic capacitor mounting structure
EP0978854A3 (en) * 1998-08-04 2007-08-01 Kabushiki Kaisha Toshiba Ceramic capacitor mounting structure
EP1104026A2 (en) * 1999-11-26 2001-05-30 Nokia Mobile Phones Ltd. Ground plane for a semiconductor chip
EP1104026A3 (en) * 1999-11-26 2003-08-13 Nokia Corporation Ground plane for a semiconductor chip

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