DE4345203C2 - Semiconductor device with improved operational speed - Google Patents

Abstract

Semiconductor device (I) comprises: (a) a semiconductor substrate (1); (b) a 'foreign' atom region (3,4) formed on the surface of (1); (c) a first semiconductor layer (6,10a) connected to the region (3,4) on the substrate (1) with an insulating film between; and (d) a second semiconductor layer (7,10b) formed along the first semiconductor layer (10a,6) and contg. 'foreign' atoms, where concn. is higher than that of the 1st layer (6,10a). Prodn. of (I) is also claimed. (I) is produced by: (a) forming a 'foreign' atom region (3,4) on the surface of the substrate (1); (b) forming an insulating film (42) having a contact opening (9a,42a) reaching the 'foreign' atom region on the surface of the substrate; (c) producing a 1st layer (6,10a) on the opening (9a,42a) and the insulating film; (d) producing a second layer (7,10b) of certain 'foreign' atom concn. on the surface of layer (6,10a); and (e) treating the second layer (7,10b) and the first layer (6,10a) by heat treating at a certain temp. for a time so that the 'foreign atoms' in the layer (7,10b) diffuse into the layer (6,10a) to bond the layer (7,10b) and the 'foreign' atom region to the surface of the substrate (1).

Description

The present invention relates to a semiconductor device with conductor layers and a manufacturing process therefor.

To carry out processing in a digital system, exist storage devices (IC memory) that binary-co store dated information or data that, as required, to be read.

IC memories are divided into different ones according to their function Groups divided, of which one DRAMs (dynamic memory with random access), the information according to the pre lie / non-existence of stored in a capacitor Save loads and which is rewritten (refresh) by Charging at constant time intervals, and that the entire Spei Lose contents when the supply voltage is switched off is (fleeting).  

A prior art semiconductor device for storing information is shown in FIG. 25. This semiconductor device includes a p-type semiconductor substrate 51 , an element isolation region 52 , word lines 55 , insulation films 70 and 71 , impurity diffusion regions 53 and 54 , a first semiconductor layer 57 which is in electrical contact with the impurity region 53 , an insulation film 61 , a semiconductor layer 58 , which is formed from polysilicon with doped n-impurity atoms along the surface of the insulation film 61 , a semiconductor layer 58 and an insulation intermediate layer 59 .

In the semiconductor device constructed as above, the word line 55 and the impurity regions 53 and 54 form a field effect transistor. Furthermore, the first semiconductor layer 57 forms a lower electrode, the insulation layer 61 forms a dielectric layer and the semiconductor layer 58 forms an upper electrode, which together form a capacitor.

As shown in FIG. 25, however, the semiconductor device built as described above is sensitive to destruction by concentration of the electric field because the capacitor has a sharp point at the circled point A. In addition, a parasitic capacitance between the word line 55 and the first semiconductor layer 57 is formed by a high impurity concentration in the first semiconductor layer 57th As a result, a word line farther from a word line driver circuit (not shown) takes more time to change levels, thereby reducing the speed of the semiconductor device. Accordingly, a parasitic capacitance is generated between the connection layer 60 and the second semiconductor layer 58 , which likewise leads to a slowdown in the operating speed of the semiconductor device.

Approaches to solving such a problem include one method to suppress the diffusion of foreign atoms in one Foreign atomic area by reducing a foreign atom concentration tion in the first semiconductor layer, and a method for Ab lower a heat treatment temperature to planarize the Interlayer insulation film. However, if the Diffu sions suppression method the foreign atom concentration of the er most semiconductor layer is reduced, becomes a resistance value the connection of the first semiconductor layer increased and min changes a capacitor capacity. The second is the planarization of the interlayer insulation film does not preclude enough so that the surface of the insulation between Layer film has stages that the formation of a compound intermediate layer adversely affected in the following steps flows. Both methods therefore lead to a deterioration of element properties.  

EP 0 496 555 A2 describes a semiconductor device with a first conductor layer, one featured on the first conductor layer see insulation layer and one on the insulation layer provided second conductor layer known. The first ladder layer has a first buffer layer of a predetermined Foreign atom concentration at an area in the area adjacent insulation layer is formed, and a first Main conductor layer, the concentration higher than that of the first Buffer layer is and which is formed on the other area.

In the post-published DE 43 00 357 A1 with earlier Priority is described a semiconductor device in which a semiconductor device has a first conductor layer, one on the first conductor layer and an insulation layer second conductor layer provided on the insulation layer points. The second conductor layer contains a second buffer layer of a predetermined impurity concentration and one second main conductor layer with another predetermined Foreign atom concentration.

It is an object of the present invention to provide a semiconductor direction of the type described in EP 0 496 555 A2 and a Manufacturing method for such a semiconductor device provide a parasitic capacitance between the first conductor layer and the second conductor layer reduced is, so that the operating speed of the semiconductor direction increased.

This object is achieved with a semiconductor device the features of claim 1 and by a method with the features of claim 3.

Preferred embodiments of the invention are in the respective Subclaims specified.  

The semiconductor device has a first and a second Conductor layer with an insulation layer in between created. The first conductor layer and the second conductor layer comprise a first and a second buffer layer on the area chen, each facing the insulation layer. Each on the sides of the first and the second buffer layer are the first and the second main layer, respectively layer formed.

In particular, the buffer layers make it possible that a pa rapid capacity between the first and second conductor layers is reduced and thus the operating speed of the half conductor device can be increased.

The following is a description of exemplary embodiments with reference to the Characters.

From the figures shows

Fig. 1 is a sectional view of a semiconductor device according to a first embodiment of the invention,

Fig. 2-18 views with the manufacturing steps of the semiconductor device of Fig. 1;

FIG. 19 is a diagram with the profile of a foreign atom concentration at a section along the line XX from FIG. 1;

FIG. 20 is a sectional view with a Halbleitervor direction according to another embodiment;

FIG. 21 is a first sectional view of a method for manufacturing the semiconductor device according to the another embodiment;

FIG. 22 is a second sectional view of a method for manufacturing the semiconductor device according to the another embodiment;

FIG. 23 shows a diagram with a profile of a foreign atom concentration along the line YY from FIG. 22;

FIG. 24 is a diagram with the profile of a foreign atom concentration of a section along the line XX from FIG. 20; and

Fig. 25 is a sectional view of a conventional memory device.

Below is a first embodiment of a DRAM that the Embodied semiconductor device, described with reference to the figures. Because the DRAM of the present Embodiment the same principle of operation as that of the conven Lichen DRAM, a description of only the different structure and manufacturing process.

The structure of a semiconductor device 40 will be described with reference to FIG. 1.

An element isolation region 2 made of SiO₂ or the like is formed on the main surface of a p-type semiconductor substrate 1 . In an active area surrounded by the element isolation region 2 , a word line 5 , which forms a first conductor layer, is formed on the main surface of the p-type semiconductor substrate 1 with an intermediate insulation film 41 made of SiO₂ or the like. The word line 5 comprises a first main conductor layer 5 a made of polysilicon or the like with phosphorus as a doped n-type impurity and an impurity concentration of about 1 × 10 ¹⁹ cm ^-3 to 1 × 10 ²¹ cm ^-3 in its lower surface, and a first Buffer layer 5 b made of polysilicon with phosphorus as a doped n-type foreign atoms with an external concentration of approximately 1 × 10 ¹⁴ cm ^-3 to 1 × 10 ¹⁹ cm ^-3 in its upper surface.

N-type impurity regions 3 and 4 with a concentration of 1 × 10¹⁷ cm ^-3 to 1 × 10²¹ cm ^-3 are formed from the surface of the p-type semiconductor substrate 1 to a predetermined depth and have the word line 5 in between.

The upper surface of the word line 5 and its side surfaces are covered with an insulation layer 42 made of SiO₂ or the like. A second conductor layer 6 made of polysilicon is formed on and along the upper side of the insulation layer 42 , with phosphorus having a concentration in the order of magnitude of 1 × 10¹⁴ cm ^-3 to 1 × 10¹⁹ cm ^-3 as doped n-type foreign atoms. The second conductor layer 6 is electrically connected to the foreign atom diffusion region 3 at a contact opening 42 a, which is provided in the insulation layer 42 .

Another second conductor layer 7 made of polysilicon with phosphorus with a concentration of the order of 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^-3 as doped n-type foreign atoms is formed along the surface of the second conductor layer 6 . An insulation layer 11 made of SiO₂ or the like is formed along the surface of the further second conductor layer 7 . Another first conductor layer 8 is formed along the surface of the insulation layer 11 .

The first semiconductor layer 8 comprises a first main conductor layer 8 a made of polysilicon with phosphorus as a doped n-type foreign atoms with a concentration of about 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^-3 in its upper surface, and a first buffer layer 8 b Polysilicon with phosphorus as a doped n-type foreign atoms with a concentration of about 1 × 10¹⁴ cm ^-3 to 1 × 10¹⁹ cm ^-3 in its upper surface.

Another second conductor layer 10 is formed on the surface of the first conductor layer 8 with an insulation layer 9 provided therebetween made of SiO 2 or the like. The second conductor layer 10 is electrically connected to the foreign atom diffusion region 4 at a contact opening 9 a, which is created in the insulation layer 9 . The second conductor layer 10 comprises a second buffer layer 10 a made of polysilicon with phosphorus as a doped n-type foreign atoms with a concentration of about 1 × 10¹⁴ cm ^-3 to 1 × 10¹⁹ cm ^-3 in its lower surface and a second main conductor layer 10 b Polysilicon with phosphorus as doped n-type foreign atoms with a concentration of about 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^-3 in its upper layer.

In the semiconductor device 40 of the arrangement described above, the word line 5 and the impurity diffusion regions 3 and 4 form a field effect transistor. Furthermore, the first conductor layer 6 and the second conductor layer 7 form a lower electrode, the insulation layer 11 forms a dielectric layer, and the further first conductor layer 8 forms an upper electrode, thus a capacitor is jointly formed.

With the arrangement described above, a semiconductor layer has a two-layer structure with foreign atom diffusion regions of low and high concentration, as shown in FIG. 1. Such a structure reduces the intensification of an electric field.

A method of manufacturing the semiconductor device 40 having the above-described structures will be described below with reference to FIGS. 2 to 17.

First, as shown in Fig. 2, an element isolation region 2 made of SiO₂ on the main surface of a p-type semiconductor substrate 1 is formed by a LOCOS method. As shown in Fig. 3, an oxide film 41 made of SiO₂ on the entire surface of the semiconductor substrate 1 is formed with a thickness of about 5.0 microns to 50.0 microns. As shown in Fig. 4, a polysilicon layer is formed as the first main conductor layer 5 a with a thickness of about 50.0 microns to 500.0 microns on the entire surface of the semiconductor substrate 1 . Then a first buffer layer 5 b made of polysilicon with a foreign atom concentration of 1 × 10¹⁴ cm ^-3 to 1 × 10¹⁹ cm ^-3 on the main conductor layer 5 a is formed.

As shown in FIG. 5, resist film 43 having a predetermined configuration is formed on the surface of the first buffer layer 5 b by photolithography. As shown in Fig. 6, the first buffer layer 5 b and the first main conductor layer 5a etched so as to have a predetermined configuration to form a word line 5 as a first conductor layer, using the resist film 43 as a mask.

As shown in FIG. 7, after removing the resist film 43, phosphorus is implanted in the main surface of the semiconductor substrate 1 using the word line 5 and the element isolation region 2 as masks to form the n-type impurity regions 3 and 4 with a concentration in on the order of 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^-3 . As shown in Fig. 8, an oxide film is applied as an insulation layer 42 made of SiO₂ on the entire surface of the semiconductor substrate 1 by the CVD method. As shown in FIG. 9, the insulation layer 42 is anisotropically etched to form a contact opening 42 a that reaches the impurity region 3 . As shown in Fig. 10, polysilicon is applied without doped foreign atoms with a thickness of about 20.0 microns-500.0 microns along the surface of the insulation layer 42 and the contact opening 42 a to form a semiconductor layer 6 a. As shown in Fig. 11, polysilicon with n-type impurities in a concentration of the order of 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^-3 is doped with a thickness of about 20.0 µm-500.0 µm applied along the surface of the semiconductor layer 6 a to form a second conductor layer 7 .

Then, as shown in FIG. 12, a resist film 21 having a predetermined configuration is formed on the surface of the second conductor layer 7 , and the semiconductor layer 6 a and the second conductor layer 7 substantially above the impurity region 4 are removed by anisotropic etching. As shown in Fig. 13, after removing the resist film 21, an insulation layer 11 made of SiO₂ or the like having a thickness of about 3.0 µm-100.0 µm is formed on the entire surface of the second conductor layer 7 by thermal oxidation. As shown in Fig. 14, a first main conductor layer 8 a made of polysilicon with phosphorus as a doped n-type impurity with a concentration of about 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^{-3 is} applied to the surface of the insulation layer 11 with a thickness of about 50.0 µm-500.0 µm. Thereafter, on the first main conductor layer 8 a a first buffer layer 8 b applied polysilicon phor with Phos as a doped n-type impurity having an impurity concen tration of 1 x 10¹⁴ cm ^-3 to 1 × 10¹⁹ cm ^-3, thereby forming an upper Elec trode is formed as the first conductor layer 8 consisting of the first main conductor layer 8 a and 8 b of the first buffer layer. Then, as shown in FIG. 15, a resist film 21 having a predetermined configuration is formed on the surface of the upper electrode 8 , and the upper electrode 8 substantially above the impurity diffusion region 4 is removed by anisotropic etching. As shown in Fig. 16 ge, an insulation layer 9 made of SiO₂ or the like is formed on the entire surface of the upper electrode 8 after the resist film 21 is removed. As shown in FIG. 17, a contact opening 9 a, which reaches the foreign atom diffusion region 4 , is formed after the sintering of the insulation layer 9 and the planarization of the surface.

Then, as shown in Fig. 18, undoped polysilicon having a thickness of about 20.0 micron 50.0 microns on the surfaces of the insulating layer 9 and the contact hole 9 a be applied, to form a second buffer layer 10 a. Thereafter, polysilicon with doped n-type foreign atoms with a concentration of about 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^-3 with a thickness of about 20.0 µm-500.0 µm, on the second buffer layer 10 a Forming a second main conductor layer 10 b applied. The second buffer layer 10 a and the second main conductor layer 10 b form a bit line as a second conductor layer 10th With the above steps, the semiconductor device 40 shown in FIG. 1 is completed.

In the embodiment described above, ions such as Si, Ge, O, C or F can be implanted in an interface between the semiconductor layer 6 a and the semiconductor substrate 1 . This serves to improve the conductivity by implanting the ions described above and to remove a thin own oxide film which is formed at the transition point.

Although in the above-described embodiment undoped polysilicon is used for the semiconductor layer 6 a and the second buffer layer 10 a, which form the bit line 10 , low-concentration polysilicon can be used to achieve the same function and effect.

While polysilicon with doped foreign atoms as a second lei layer is applied, the same function and us can be achieved by doping foreign atoms into the bottom lysilicon during application.

Although an n-type impurity diffusion region in a p-type half conductor substrate in each of the above-described embodiments a p-type impurity diffusion region in one n-type semiconductor substrate are formed, and the same function and achieve effect.

Another embodiment is described below. In the first embodiment described above, an undoped polysilicon layer or a polysilicon layer with low-concentration impurities of the same line type (n-type in the first embodiment) as that of the impurity diffusion region on the semiconductor layer 6 a and the second buffer layer 10 a of the bit line 10 is applied . In the present embodiment, a polysilicon layer with doped foreign atoms of the opposite conductivity type as that of the foreign atom diffusion region is applied to the semiconductor layer 6 a and the second buffer layer 10 a.

Fig. 20 is a sectional view with the semiconductor device 45 thus manufactured. Since the structure of the device is the same as that of Fig. 1, description will not be repeated.

A method of manufacturing a semiconductor device according to the present embodiment will be described below.

The method has the same steps for forming the contact hole 42 a on the interlayer insulation film 42 to reach the impurity diffusion region as described in the first embodiment and as shown in FIGS. 2 to 9. Therefore, these steps are not described again.

Then, as shown in Fig. 21, p-type impurity polysilicon having a concentration of about 1 × 10¹⁴ cm ^-3 to 1 × 10²¹ cm ^-3 is doped along with a thickness of 20.0 µm to 500.0 µm the surfaces of the insulation film 42 and the contact opening 42 a to form a semiconductor layer 6 a applied. As shown in Fig. 22, n-type impurity polysilicon with a concentration of 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^-3 is doped with a thickness of 20.0 µm to 500.0 µm along the surface the first semiconductor layer 6 a applied to form a second conductor layer 7 .

A profile of the impurity concentration on a section along the line YY in the figure at this time is shown in FIG. 23. After that, by the same steps as in the first embodiment, the semiconductor device having the sectional structure shown in FIG. 20 can be formed.

The semiconductor device 45 thus formed has a impurity concentration profile at the portion along the line XX of FIG. 20 as shown in FIG. 24, which shows that the device can be formed without increasing a transition depth of the impurity region 3 .

Accordingly, the second buffer layer 10 a, which forms the connecting layer of the further embodiment, can achieve the same function and effect by using a polysilicon layer with foreign atoms of the opposite conductivity type as that of the foreign atom diffusion region 4 .

Although in the respective embodiments, the foreign atoms in the second conductor layer 7 are reduced by diffusion, the amount of the diffused foreign atoms from the second semiconductor layer is much smaller than that of the foreign atoms contained in the second semiconductor layer. Therefore, it is believed that the impurity concentration of the second conductor layer is not affected.

Furthermore, the semiconductor device has a first conductor layer and a second conductor layer with one in between provided insulation film provided. The first ladder layer and the second conductor layer has a first and a second puff layer on the insulating film adjacent areas. On the opposite sides of each buffer layer for insulation a first and a second main line layer.

Such a measure reduces parasitic capacitance between the first conductor layer and the second conductor layer and increases an operation speed of the semiconductor device tung.

Claims (6)

1. semiconductor device with
a first conductor layer ( 5 , 8 ),
an insulation layer ( 9 , 42 ) provided on the first conductor layer ( 5 , 8 ),
a second conductor layer ( 6 and 7 , 10 ) provided on the insulation layer ( 9 , 42 ),
the first conductor layer ( 5 , 8 )
has a first buffer layer ( 5 b, 8 b) of a predetermined impurity concentration, in a region in the vicinity adjacent to the insulation layer ( 9 , 42 ), and
a first main conductor layer ( 5 a, 8 a), the concentration of which is higher than that of the first buffer layer ( 5 b, 8 b) and which is formed on the other region, and
the second conductor layer ( 6 and 7 , 10 )
a second buffer layer ( 6 , 10 a) of a predetermined impurity concentration, which is formed in a region in the vicinity adjacent to the insulation layer ( 9 , 42 ), and
has a second main conductor layer ( 7 , 10 b), the foreign atom concentration of which is higher than that of the second buffer layer ( 6 , 10 a), in the other region. 2. Semiconductor device according to claim 1, characterized in that the first buffer layer ( 5 b, 8 b) and the second buffer layer ( 6 , 10 a) have a foreign atom concentration of 1 × 10¹⁴ cm ^-3 to 1 × 10¹⁹ cm ^-3 , and the first main conductor layer ( 5 a, 8 a) and the second main conductor layer ( 7 , 10 b) have a foreign atom concentration of 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^-3 . 3. A method for producing the semiconductor device according to claim 1, comprising the steps:
Forming an impurity region ( 3 , 4 ) on a main surface of a semiconductor substrate ( 1 ),
Forming an insulation film ( 42 ) with a contact opening ( 9 a, 42 a) that reaches the impurity region on the main surface of the semiconductor substrate ( 1 ),
Forming the second buffer layer ( 6 , 10 a) on the surfaces of the contact opening ( 9 a, 42 a) and the insulation film ( 42 ),
Forming the second main conductor layer ( 7 , 10 b) with a pre-determined impurity concentration on the surface of the second buffer layer ( 6 , 10 a), and
Treating the second main conductor layer ( 7 , 10 b) and the second buffer layer ( 6 , 10 a) with a heat treatment at a predetermined temperature for a predetermined time, so that the foreign atoms contained in the second main conductor layer ( 7 , 10 b) diffuse in and pass through the second buffer layer ( 6 , 10 a) to connect the second Hauptlei layer ( 7 , 10 b) and the impurity region ( 3 , 4 ) on the main surface of the semiconductor substrate ( 1 ). 4. A method of manufacturing a semiconductor device according to claim 3, characterized in that
the second buffer layer ( 6 , 10 a) is formed from undoped polysilicon and
the second main conductor layer ( 7 , 10 b) is formed from polysilicon into which foreign atoms with a concentration of 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^{-3 are} doped. 5. A method for producing a semiconductor device according to claim 3 or 4, characterized in that the step of forming the second buffer layer ( 6 , 10 a) comprises a step of depositing polysilicon with doped foreign atoms, the conductivity of which is opposite to that of the foreign atoms in the foreign atom region ( 3 , 4 ). 6. A method of manufacturing a semiconductor device according to any one of claims 3 to 5, characterized by the steps
Form an insulation layer ( 11 ) on the second main layer ( 7 , 10 b) and
Forming a third layer ( 8 ) with a predetermined foreign atom concentration on the insulation layer ( 11 ).