DE4307575C2 - Semiconductor device and manufacturing method therefor - Google Patents

Description

The present invention relates to a semiconductor device according to the preamble of claim 1 and a manufacturing process therefor.

To carry out processing in a digital system, exist storage devices (IC memory) that binary-co store dated information or data that, as required, to be read.

IC memories are divided into different ones according to their function Groups divided, of which one DRAMs (dynamic memory with random access), the information according to the pre lie / non-existence of stored in a capacitor Save loads and which is rewritten (refresh) by Charging at constant time intervals, and that the entire Spei Lose contents when the supply voltage is switched off is (fleeting).

As shown in FIG. 21, the DRAM essentially consists of a memory cell array 100 with a plurality of semiconductor memory devices, an X decoder 110 and a Y decoder 120 , which are necessary for input / output, and an input / output Control circuit 130 .

As shown in Fig. 22, the semiconductor memory devices 140 in the memory cell array 100 are at intersection points between a plurality of word lines WL₁, WL₂,. . . WL _n , which extend in a row direction, and a plurality of bit lines BL₁, BL₂,. . . BL _n , which he stretch in a column direction, arranged.

As shown in Fig. 21, an address signal for designating a position of a desired semiconductor device 140 from an X address 110 a and a Y address 120 a is applied. A writing and reading of the desired semiconductor device 140 is performed by an input / output control signal 130 a. The X decoder 110 and the Y decoder 120 are circuits for selecting an address using an address signal.

The semiconductor device 140 described above is a memory for storing information corresponding to the presence / absence of charges to be stored in a capacitor. Fig. 23 shows an equivalent circuit of Halbleitervorrich tung 140th The semiconductor device 140 comprises a field effect transistor 150 and a capacitor 160 . The reading is performed by determining the presence / absence of charges in the capacitor 160 , by a current flowing through a capacitance C _{d of} a precharged bit line to the field effect transistor 150 .

FIG. 24 is a plan view of the memory cell array 100. Bit lines 60 are arranged in a column direction such that they come into contact with foreign atom diffusion areas 54 at bit line contact areas 60 a, which are provided on a semiconductor substrate 51 . Word lines 50 are provided in a row direction.

As shown in FIG. 25, an internal structure of the semiconductor memory device 140 will be described. Fig. 25 is a sectional view taken along the line XX of Fig. 24.

An element isolation region 52 is formed on a main surface of a p-type semiconductor substrate 51 . In an active region surrounded by the element isolation region 52 , a word line 55 is formed on the main surface of the p-type semiconductor substrate 51 via an insulation film 70 . N-type impurity regions 53 and 54 are formed down from the surface of the P-type semiconductor substrate 51 to a predetermined depth, at a position where the regions include the above word line 55 .

The upper surface and the side surfaces of the word line 55 are covered with an insulation film 71 . On the upper surface of the insulation film 71 , a first semiconductor layer made of polysilicon is formed, in the surface of which n-type impurities are doped. The first semiconductor layer 57 is electrically connected to the impurity region 53 at a contact point (contact hole) 71 a, which is provided in the insulation film 71 .

An insulation film 61 made of an oxide film is formed along the surface of the first semiconductor layer 57 . A third semiconductor layer 58 made of polysilicon with doped n-type impurities is formed along the surface of the insulation film 61 . A connection layer 60 with an intermediate insulation layer 59 is formed on the surface of the third semiconductor layer 58 . The connection layer 60 is electrically connected to the impurity region 54 at a contact opening 59 a, which is formed in the interlayer insulation film 59 ge.

In the semiconductor device 140 constructed as above, the word line 55 and the impurity regions 53 and 54 form a field effect transistor. Furthermore, the first semiconductor layer 57 forms a lower electrode, the insulation layer 66 a dielectric layer, and the third semiconductor layer 58 forms an upper electrode, which together form a capacitor.

A method of manufacturing the semiconductor device 140 according to the structure described above will be described below with reference to FIGS. 26 to 40.

First, as shown in FIG. 26, an element isolation region 52 is formed on a main surface of a p-type semiconductor substrate 51 by a LOCOS method. As shown in FIG. 27, an oxide film 70 is formed on the entire main surface of the semiconductor substrate 51 . As shown in Fig. 28, a polysilicon layer 55 a is formed on the entire surface of the semiconductor substrate 51 . As shown in Fig. 29, a resist film 72 is formed with a predetermined configuration on the surface of the polysilicon layer 55 a by photolithography. As shown in Fig. 30, the polysilicon layer 55 a and the oxide film 70 are anisotropically etched by using the resist film 72 as a mask to form a word line 55 .

Then, as shown in FIG. 31, after removing the resist film 72, phosphorus is diffused into the main surface of the semiconductor substrate 51 by using the word line 55 and the element isolation region 52 as masks to form n-type impurity regions 53 and 54 . As shown in Fig. 32, an oxide film 71 is deposited on the entire surface of the semiconductor substrate 51 by the CVD method. As shown in FIG. 33, the oxide film 71 is etched by anisotropic etching or the like to form a contact hole 71 a in contact with the impurity region 53 .

Then, as shown in FIG. 34, polysilicon with highly concentrated phosphorus is applied along the surfaces of the insulation film 71 and the contact opening 71 a to form a first semiconductor layer 57 . As shown in FIG. 35, a resist film 21 of a predetermined configuration is formed on the surface of the first semiconductor layer 57 , and the first semiconductor layer 57 substantially above the impurity region 54 is removed by anisotropic etching. As shown in FIG. 36, after removing the resist film 21, an insulation layer 61 consisting of an oxide film is applied to the entire upper surface of the first semiconductor layer 57 . As shown in FIG. 37, a second semiconductor layer 58 made of polysilicon with highly concentrated phosphorus is formed on the surfaces of the insulation layer 61 and the oxide film 71 .

Then, as shown in FIG. 38, a resist film 22 having a predetermined configuration on the surface of the second semiconductor layer 58 are formed, and the second semiconductor layer 58 is substantially above the impurity region 54 is removed by anisotropic etching. As shown in FIG. 39, after removing the resist film 22, an interlayer insulating film 59 is formed on the entire surface of the second semiconductor layer 58 . As shown in Fig. 40, after the Sin a tern the impurity region 54 reach the contact opening 59 a by photolithography or the like of the interlayer insulating film 59 and the planarization of the surface. Thereafter, a semiconductor device 140 shown in FIG. 25 is completed by forming a compound layer 60 made of polysilicon or the like on the surface of the interlayer insulating film 59 and in the contact hole 59a.

As shown in FIG. 40, however, the semiconductor device built as described above is sensitive to destruction by concentration of the electric field because the capacitor has a sharp point at the circled point A. In addition, a parasitic capacitance between the word line 55 and the first semiconductor layer 57 is formed by a high impurity concentration in the first semiconductor layer 57th As a result, a word line farther from a word line driver circuit (not shown) takes more time to change levels, thereby reducing the operation speed of the semiconductor device. Accordingly, a parasitic capacitance is generated between the connection layer 60 and the second semiconductor layer 58 , which likewise leads to a slowdown in the operating speed of the semiconductor device.

On the other hand, impurities contained in the first impurity layer diffuse into an impurity region through a heat treatment step during the manufacturing process, thereby increasing a depth of diffusion of the impurity region on the surface of the substrate. As shown in Figs. 36 to 40, it is clear that the impurity diffusion area is significantly increased in the respective steps. Particularly in the case of a heat treatment for planarization of the interlayer insulation film 59 , foreign atoms diffuse deep into the substrate, even through a gentle heat treatment that is carried out at about 850 ° C. for two hours. Fig. 41 shows the profile of an impurity concentration taken along the line XX in Fig. 25. The lower the impurity region in the substrate is, the narrower the distance between the impurity region and a third is nuclear area of the adjacent element, as shown in Fig. 42 is shown. As a result, depletion layers 80 formed at the junctions of the impurity diffusion region cause breakdown, resulting in deterioration in semiconductor element characteristics and memory defects.

Approaches to solving such a problem include a metho de to suppress the diffusion of foreign atoms into egg a foreign atomic region by reducing a foreign atom concentration tion in the first semiconductor layer, and a method for Ab lower a heat treatment temperature to planarize the Interlayer insulation film. However, if the Diffu sions suppression method the foreign atom concentration of the er most semiconductor layer is reduced, becomes a resistance value the connection of the first semiconductor layer increased and min changes a capacitor capacity. The second is the planarization of the interlayer insulation film does not preclude enough so that the surface of the insulation between Layer film has stages that the formation of a compound intermediate layer adversely affected in the following steps flows. Both methods therefore lead to a deterioration of element properties.  

EP 0 496 555 A2 describes a semiconductor device according to the The preamble of claim 1 is known. The semiconductors direction has a storage capacitor, one elec trode consists of the first and second semiconductor layers. There the first and second semiconductor layers different foreign have atomic concentrations, one exists during the Manufacturing process occurring heat treatment the risk that in particular from the higher doped semiconductor layer Diffuse foreign atoms into unwanted areas.

A semiconductor device is described in DE 43 00 357 A1 ben, which has a stacked capacitor. The lower electrode of the stack capacitor is with a doped region in the Semiconductor substrate connected. To avoid thermal Diffusion of foreign atoms from the lower capacitor electrode is in the doped area in the semiconductor substrate polycrystalline silicon layer with a relatively small Impurity concentration between the lower capacitor electrode and the doped region in the semiconductor substrate.

It is therefore an object of the invention to provide a semiconductor device the type described above so that the diff sion of foreign atoms between a semiconductor layer and a Foreign atomic area is suppressed improved.

This object is achieved by a semiconductor device type described at the outset, which is characterized by the characteristic Merk male of claim 1 is characterized.

The problem is also solved by a method for manufacturing Position of such a semiconductor device with the Merkma len of claim 6.

Preferred embodiments of the invention result from the associated subclaims.  

The procedure for Manufacturing the semiconductor device has a step of forming a separate oxide film between the first layer and the second semiconductor layer on what further diffusion of the foreign atoms of a lower electrode in the foreign atom area in a Heat treatment of a relevant manufacturing step under presses, thereby preventing expansion of the foreign atom region becomes.

The following is a description of exemplary embodiments with reference to FIG Characters.

Show from the figures

Fig. 1 is a sectional view of a Halbleitervorrich tung for explaining the background of the invention;

Fig. 2-18 views with the manufacturing steps of the semiconductor device of Fig. 1 in a manufacturing process;

FIG. 19 is a diagram with the profile of a foreign atom concentration at a section along the line XX from FIG. 1;

FIG. 20 is a sectional view of a Halbleitervorrich processing according to an embodiment of the invention;

Fig. 21 is a schematic diagram showing the basic structure of a DRAM,

FIG. 22 is a schematic diagram showing the arrangement of a semiconductor device in a Lenfeld Speicherzel;

FIG. 23 is a diagram showing an equivalent circuit of the semiconductor device;

FIG. 24 is a diagram showing a planar configuration of the memory cell array;

Fig. 25 is a diagram showing a sectional arrangement of a conventional memory device;

Fig. 26-40 views showing the manufacturing steps ei nes conventional manufacturing method;

FIG. 41 is a view showing a profile of an impurity concentration of a section taken along the line XX of Fig. 25; and

Fig. 42 is a schematic diagram for illustrating the deterioration of element characteristics due to an expansion of a Diffusionsbe kingdom in a semiconductor substrate.

The following is an embodiment of a DRAM described with reference to the figures. Because the DRAM of the present Embodiment the same principle of operation as that of the conventional Lichen DRAM, a description of only the different structure and manufacturing process.

The structure of a semiconductor device 40 will be described with reference to FIG. 1.

An element isolation region 2 made of SiO₂ or the like is formed on the main surface of a p-type semiconductor substrate 1 . In an active area surrounded by the element isolation region 2 , a word line 5 is formed on the main surface of the p-type semiconductor substrate 1 with an intervening insulation film 41 made of SiO 2 or the like. The word line 5 comprises a main conductor layer 5 a made of polysilicon or the like with phosphorus as a doped n-type impurity and an impurity concentration of about 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^-3 in its lower surface, and a buffer layer 5 b made of polysilicon with phosphorus as a doped n-type foreign atoms, with an external concentration of about 1 × 10¹⁴ cm ^-3 to 1 × 10¹⁹ cm ^-3 in its upper surface.

N-type impurity regions 3 and 4 with a concentration of 1 × 10¹⁷ cm ^-3 to 1 × 10²¹ cm ^-3 are formed from the surface of the p-type semiconductor substrate 1 to a predetermined depth and have the word line 5 in between.

The upper surface of the word line 5 and its side surfaces are covered with an insulation film 42 made of SiO₂ or the like. On and along the upper side of the insulation film 42 , a first semiconductor layer 6 made of polysilicon with phosphorus having a concentration of the order of 1 × 10¹⁴ cm ^-3 to 1 × 10¹⁹ cm ^{-3 is formed} as a doped n-type impurity. The first conductor layer 6 is electrically connected to the foreign atom diffusion region 3 at a contact opening 42 a, which is provided in the insulation film 42 .

A second conductor layer 7 made of polysilicon with phosphorus with a concentration of the order of 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^-3 as doped n-type foreign atoms is formed along the surface of the first conductor layer 6 . An insulation layer 11 made of SiO₂ or the like is formed along the surface of the second conductor layer 7 . A third semiconductor layer 8 is formed along the surface of the insulation layer 11 .

The third semiconductor layer 8 comprises a main conductor layer 8 a made of polysilicon with phosphorus as doped n-type foreign atoms with a concentration of about 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^-3 in its upper surface and a buffer layer 8 b made of polysilicon Phosphorus as a doped n-type foreign atoms with a concentration of about 1 × 10¹⁴ cm ^-3 to 1 × 10¹⁹ cm ^-3 in its upper surface.

A connection layer 10 is formed on the surface of the third semiconductor layer 8 with an intermediate insulation film 9 provided therebetween made of SiO₂ or the like. The connection layer 10 is electrically connected to the Fremdatomdiffu sion region 4 at a contact opening 9 a, the rule insulating film in Zvi 9 is provided. The connection layer 10 comprises a buffer layer 10 a made of polysilicon with phosphorus as a doped n-type foreign atoms with a concentration of about 1 × 10¹⁴ cm ^-3 to 1 × 10¹⁹ cm ^-3 in its lower surface and a main conductor layer 10 b made of polysilicon with phosphorus as a doped n-type foreign atoms with a concentration of about 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^-3 in its upper layer.

In the semiconductor device 40 of the arrangement described above, the word line 5 and the impurity diffusion regions 3 and 4 form a field effect transistor. Furthermore, the first conductor layer 6 and the second conductor layer 7 form a lower electrode, the insulation layer 11 forms a dielectric layer, and the third semiconductor layer 8 forms an upper electrode, thus a capacitor is jointly formed.

With the arrangement described above, a semiconductor layer has a two-layer structure on the part denoted by A in FIG. 40, with foreign atom diffusion regions of low and high concentration, as shown in FIG. 1. Such a structure reduces the intensification of an electric field.

A method of manufacturing the semiconductor device 40 having the above-described structures will be described below with reference to FIGS. 2 to 17.

First, as shown in Fig. 2, an element isolation region 2 made of SiO₂ on the main surface of a p-type semiconductor substrate 1 is formed by a LOCOS method. As shown in Fig. 3, an oxide film 41 of SiO₂ is formed on the entire surface of the semiconductor substrate 1 with a thickness of about 50 Å to 500 Å. As shown in Fig. 4, a polysilicon layer 5 a is formed with a thickness of about 50 nm to 500 nm of the entire surface of the semiconductor substrate 1 . Then a buffer layer 5 b of polysilicon with a foreign atom concentration of 1 × 10¹⁴ cm ^-3 to 1 × 10¹⁹ cm ^-3 on the main layer 5 a is formed.

As shown in Fig. 5, resist film 43 having a vorbestimm th configuration on the surface of the buffer layer 5b formed by photolithography. As shown in Fig. 6, the buffer layer 5b, and the main conductor layer 5a, so as to have a predetermined configuration to form a word line 5 is etched using the resist film 43 as a mask.

As shown in FIG. 7, after removing the resist film 43, phosphorus becomes in the main surface of the semiconductor substrate 1 using the word line 5 and the element isolation region 2 as masks for forming the n-type impurity regions 3 and 4 with a concentration of the order implanted from 1 × 10¹ ^-3 cm ^-3 to 1 × 10²¹ cm ^-3 . As shown in Fig. 8, an oxide film 42 made of SiO₂ is applied to the entire surface of the semiconductor substrate 1 by the CVD method. As shown in Fig. 9, the insulation film 42 is anisotropic to form a contact opening 42 a, which reaches the impurity region 3 . As shown in Fig. 10, polysilicon without doped foreign atoms with a thickness of about 20 nm-500 nm is applied along the surface of the insulation film 42 and the contact opening 42 a to form a first semiconductor layer 6 a. As shown in Fig. 11, polysilicon with n-type impurities in a concentration of the order of 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^-3 is doped with a thickness of about 20 nm-500 nm along the surface of the first semiconductor layer 6 a applied to form a second semiconductor layer 7 .

Then, as shown in FIG. 12, a resist film 21 having a predetermined configuration on the surface of the second semiconductor layer 7 is formed, and the first semiconductor layer 6a and the second semiconductor layer 7 substantially above the impurity region 4 are removed by anisotropic etching. As shown in Fig. 13, after removing the resist film 21, an insulation layer 11 made of SiO₂ or the like having a thickness of about 3 nm-100 nm is formed on the entire surface of the second semiconductor layer 7 by thermal oxidation. As shown in Fig. 14, a main conductor layer 8 a made of polysilicon with phosphorus as a doped n-type impurity with a concentration of about 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^-3 on the surface of the insulating film 11 with a Thickness of about 50 nm-500 nm applied. Thereafter, on the main conductor layer 8 a, a buffer layer 8 b of polysilicon Phos phor as a doped n-type impurity having an impurity concen tration of 1 x 10¹⁴ cm ^-3 to 1 × 10¹⁹ cm ^-3 applied, whereby an upper Elec trode 8 is formed which consists of the main conductor layer and the buffer layer 8 a 8 b. Then, as shown in FIG. 15, a resist film 21 having a predetermined configuration is formed on the surface of the upper electrode 8 , and the upper electrode 8 substantially above the impurity diffusion region 4 is removed by anisotropic etching. As shown in Fig. 16 ge, an interlayer insulation film 9 made of SiO₂ or the like is formed on the entire surface of the upper electrode 8 after the resist film 21 is removed. As shown in FIG. 17, a contact opening 9 a, which reaches the foreign atom diffusion region 4 , is formed after the sintering of the insulating interlayer film 9 and the planarization of the surface.

Then, as shown in Fig. 18, undoped polysilicon having a thickness of about 20 nm-50 nm on the surfaces of the interim rule insulation film 9 and the contact hole 9 a for forming a buffer layer 10a applied. Thereafter, polysilicon with doped n-type foreign atoms with a concentration of about 1 × 10¹⁹ to 1 × 10²¹ cm³ with a thickness of about 20 nm-500 nm is applied to the buffer layer 10 a to form a main conductor layer 10 b. The buffer layer 10 a and the main conductive layer 10 b form a bit line 10th With the above steps, the semiconductor device 40 shown in FIG. 1 is completed.

As described above, the provision of the first semiconductor layer 6 a can suppress diffusion of the foreign atoms from the second semiconductor layer 7 into the foreign atom region 3 .

The reason is as follows. In order to diffuse the high doping concentration of phosphorus in the second semiconductor layer in the Fremdatomdiffu sion section 3, the phosphor by the first semiconductor layer 6 with a not-doped impurities out by diffuse would. This is equivalent to a situation where an impurity diffusion source is located away from the substrate. Therefore, with the same heat treatment, a smaller amount of foreign atoms than the conventional case reaches the substrate, which enables a transition with a desired depth.

FIG. 19 shows the graph of a profile of a foreign atom concentration at a portion along the line XX in a transition region with the foreign atom diffusion region 3 from FIG. 18. Compared to FIG. 41, where the profile of a conventional foreign atom concentration was shown as described above of FIG. 19 shows that a junction depth of the impurity atoms and is reduced. This also applies to the transition area of the bit line 10 with the impurity diffusion area 4 .

As a result, the first conductor layer 6 a and the buffer layer 10 a conductive by the diffusion of impurity from the second semiconductor layer 7 and the main conductive layer 10 b and permit an electrical junction between the first semiconductor layer 6 and the impurity diffusion region 3 and the between the main conductor layer 10 b and the foreign atom diffusion area 4 .

An embodiment of the semiconductor according to the invention is described below direction described.

As shown in FIG. 20, compared to the arrangement of the first embodiment described above, an oxide film 30 is formed between a first semiconductor layer and a second semiconductor layer. The provision of the oxide film allows further diffusion of the foreign atoms from the second semiconductor layer to be suppressed.

As shown in FIG. 10, in a method for producing the oxide film 30, a first semiconductor layer 6 a is formed in this case and then left in an atmosphere for approximately 1 hour to form a separate oxide film with a thickness of approximately 1 nm. This is because the conductivities of the first semiconductor layer and the second semiconductor layer can be obtained because a polysilicon layer is deposited in cavities such as pinholes in an oxide film of uneven thickness.

Even without such holes, if the oxide film has a thickness of about 1 nm, a tunnel current flows and makes the first and the second semiconductor layer is conductive with one another (brings it into Connection).

The arrangement described above can provide the same function and effect as the embodiment described above. Although a description has been made above for a case where the oxide film 30 is provided between the first and second semiconductor layers, the same function and effect can be achieved by correspondingly forming an oxide film between the buffer layer 10 a and the main conductor layer 10 b form the bit line 10 is created.

In each of the above-described embodiments, ions such as Si, Ge, O, C or F can be implanted in an interface between the first semiconductor layer 6 a and the semiconductor substrate 1 . This serves to improve the conductivity by implanting the ions described above and to remove a thin own oxide film which is formed at the transition point.

Although undoped polysilicon is used for the first semiconductor layer 6 a and the buffer layer 10 a, which form the bit line, in the above-described embodiments, low-concentration polysilicon can be used to achieve the same function and effect.

While polysilicon with doped foreign atoms as a second lei layer is applied, the same function and us can be achieved by doping foreign atoms into the bottom lysilicon during application.

Although an n-type impurity diffusion region in a p-type half conductor substrate in each of the above-described embodiments a p-type impurity diffusion region in one n-type semiconductor substrate are formed, and the same function and achieve effect.

Claims (7)

1. semiconductor device with
a semiconductor substrate ( 1 ),
a foreign atom region ( 3 , 4 ) formed in a main surface of the semiconductor substrate ( 1 ),
a first semiconductor layer ( 6 ) which is connected to the foreign atom regions ( 3 , 4 ) and is formed on the semiconductor substrate ( 1 ) with an insulation film ( 32 ) provided therebetween and has foreign atoms of a predetermined concentration, and a second semiconductor layer ( 7 ) which is formed along the first semiconductor layer ( 6 ) and has foreign atoms whose concentration is higher than that of the first semiconductor layer ( 6 ),
characterized by an oxide film ( 30 ) between the first semiconductor layer ( 6 ) and the second semiconductor layer ( 7 ), the thickness of which is selected such that a tunnel current between the two semiconductor layers ( 6 , 7 ) is possible. 2. The semiconductor device according to claim 1, characterized in that the oxide film has a thickness of 0.5 to 2.0 nm, in particular 1 nm. 3. The semiconductor device as claimed in claim 1 or 2, characterized by an insulation layer ( 11 ) which is formed along the surface of the second semiconductor layer ( 7 ), and a third semiconductor layer ( 8 ) which has foreign atoms whose concentration is higher than that of the first Is semiconductor layer ( 6 ) and which is formed along the surface of the insulation layer ( 11 ). 4. A semiconductor device according to claim 3, characterized in that the first semiconductor layer ( 6 ), the second semiconductor layer ( 7 ), the insulation layer ( 11 ) and the third semiconductor layer ( 8 ) form a capacitor. 5. Semiconductor device according to claim 3 or 4, characterized in that the first semiconductor layer ( 6 ) is formed from a polysilicon layer which has foreign atoms of a concentration in the range between 1 × 10¹⁴ cm ^-3 to 1 × 10¹⁹ cm ^-3 ,
the second semiconductor layer ( 7 ) is formed from a polysilicon layer which has foreign atoms with a concentration in the range between 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^-3 , and
the third semiconductor layer ( 8 ) is formed from a polysilicon layer which has foreign atoms with a concentration in the range between 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^-3 . 6. A method of manufacturing the semiconductor device according to claim 1, comprising the steps of:
Forming the foreign atom region ( 3 , 4 ) in the main surface of the semiconductor substrate ( 1 ),
Forming the insulation film ( 42 ) with a contact opening ( 42 a) which reaches the impurity region in the main surface of the semiconductor substrate ( 1 ),
Forming the first semiconductor layer ( 6 ) on the surface of the contact opening ( 42 a) and the insulation film ( 42 ),
Forming the oxide film ( 30 ) by exposing the first semiconductor layer ( 6 ) to an atmosphere for a predetermined period of time, and
Forming the second semiconductor layer ( 7 ) with a predetermined impurity concentration. 7. The method according to claim 6, characterized in that the first layer ( 6 ) is formed from undotier tem polysilicon, and the second layer ( 7 ) is formed from polysilicon, in the foreign atoms of a concentration of 1 × 10¹⁹ cm ^-3 to 1 × 10²¹ cm ^{-3 are} doped.