DE4335879A1 - Arrangement for quality control and monitoring of through-plated multilayer printed circuit boards - Google Patents

Abstract

An arrangement for quality control and monitoring of through-plated multilayer printed circuit boards, at least one monitoring loop being formed in the multilayer printed circuit board, which loop has at least one residual ring whose geometrical size is reduced at least in comparison with residual rings which are not located in a monitoring loop on the multilayer printed circuit board.

Description

The invention relates to an arrangement in the preamble of claim 1 specified Art.

Such arrangements are used for multilayer circuits (so-called multilayer boards) in electrical and electronic  devices and systems required to ensure reliable Control of the full functionality of the Allow circuit boards.

Such a quality control is both as a manufacturing Final inspection after the manufacture of the drilled conductors plates as well as incoming inspection in front of each other steps of through-plating the multilayer sensible.

In addition, it is in stoned areas of application the multilayer as ongoing monitoring during loading it makes sense to avoid line interruptions due to Cor rosion, thermal overuse in areas of Through-plating or the like to be recorded immediately in order to turn it right resulting further damage due to overuse of Avoid components or incorrect functioning.

Multilayer circuits or multilayers are the largest today partly step by step by joining copper foils and insulating layers made by lamination, wherein usually first individual shift groups (intermediate laminates) and finally made from them the multilayer circuit board with the required total number of layers is built up.

The overall structure according to the prior art is explained with reference to FIG. 2.

First, for a multilayer printed circuit board 1, an energy core basic assembly 2 consisting of several prepreg layers is laminated on both sides by laminating a relatively thick copper foil and carrying out a subtractive etching process in which the copper foil is etched off in all areas not covered with a photoresist, and thus the printed scarf tion is formed.

This energy core 2 serves as the basis for the construction of signal levels 3 by repeatedly laminating further layers of prepreg and (much thinner) copper foil, which is again structured on the way via a resist mask exposure, after exposure by semi-additive copper plating in the copper bath When developing exposed sections - depending on the length of stay - additional copper is grown. The resulting (reinforced) conductor tracks 3 a, 3 b are additionally protected with a tin covering, and then, after removal of the photoresist mask, the copper foil is coated on the entire surface, with the exception of the reinforced areas 3 a protected by the tin layer, 3 b away.

In this way, so-called residual rings 4 a, 4 b, that is to say areas with circular circles, are also provided in the conductor tracks at the locations provided on the outer surfaces 1 a, 1 b of the laminate 1 for the subsequent contacting of components or through-contacting of the individual levels. or elliptically enlarged width and greater thickness than the actual conductor tracks. The larger thickness of the rings is u. U. also realized in a special resist-etching step.

The remaining rings serve to ensure a gu th contact between the conductive inner coating of the  Walls of the via holes to be created later Holes and the associated conductor lines in the level of the printed circuit board, even with a slight defect alignment between holes and conductor tracks.

To form plated-through regions, holes 5 are introduced into the laminate nat 1 and then the walls 5 a of these holes 5 with an inside of all where holes for connecting signal planes are to be created, for example by means of a multi-spindle drilling device or laser beams -Coppering 6 provided.

Alternatively, the via areas can also be opened other way including photo etching be fathered.

In this case, on the outer layer 1 a, 1 b of the multilayer structure, the copper foil is first removed by the photo-etching step at the locations provided for the holes, then the holes 5 are made by laser, and finally are copper-plated in a further photo-etching step and by semi-additives Signal lines 3 c generated and at the same time copper-plated the bore walls 5 a.

In these methods - as schematically sketched in Fig. 3 (a) and (b) - the possibility of misalignments of the holes 5 with their inner wall coating 6 compared to the residual rings 4 a, 4 b and the holes 5 together with the residual rings 4 a, 4 b compared to the conductor lines 3 c, 3 d as a result of incorrect positioning of the laminate 1 in successive process steps, with the result that there is insufficient contact between the individual interconnect sections - in particular between the inner wall coating and the actual conductor line - al so that the through-connection is interrupted in places from the beginning or there is an acute risk of interruptions due to - even minor - corrosion in operation.

This results in the need for a quality check after production or a relevant production level and / or monitoring of the multi-layer ladder plates under special consideration during operation through-hole areas.

In the known, especially for the testing of wire pull gene provided on one level of a circuit board PCB test devices currently dominate the optical Verification.

In this way, a comparison with a standard alternates in the steroscopic beam path the test specimen and then the Standard presented, as for example in the DE-OS 25 30 750 is described.

A computer-based is also known from DE-OS 35 40 100 Testing of printed circuit boards using the optical design Rule check for functional errors.

From DD-PS 2 37 382 it is also known that ausgangssei with a bus and on the input side with an encoder coupled input circuits for measuring the encoder signal and used for surveillance.  

From DE-OS 28 21 821 it is finally known that completely presence of a number of assemblies in one Switching by means of one hand on a ladder board side as conductor track or wire bridge and others on the PCB insertion side (connector side) provided, including each assembly, including existing, normal conductor tracks predetermined current to monitor the path.

These solutions are for testing multilayer circuits gene with the features described above in terms of Possible errors mentioned are not suitable.

Using the latter solution would be particularly special secured in no way that with a deviation the position of the holes or another - for example due to corrosion - errors especially for testing predetermined current path is interrupted.

Because of the bore tolerances, the tolerances in the Dimensions of the residual rings and especially the offset individual levels against each other when layering it can to interruptions in the area of the plated-through holes that do not necessarily lead to interruptions of the lead to the test of the specified current path and therefore at the test went undetected. On the other hand, that reacts Procedure of course (as primarily intended) on the Absence of an assembly with an intact multilayer, i. H. the Error message is unspecific regarding the ladder plate function.  

Some of the known solutions are complex, and they ge equip only the final production inspection or the inspection upon receipt of goods, but no monitoring of the circuit board during operation.

Above all, however, they are not for multi testing Layer circuit boards can be used.

They are solutions for quick and easy cable or Line test known, in which either a moni Ohmic resistance takes place or in those a capacitive signal into the cable during operation is fed in and decoupled.

So from DD-PS 1 39 307 a corresponding arrangement for Locating wire breaks in plastic-insulated single wires knows. However, this solution is highly specific to the Qua Liability monitoring during the manufacture of an isolated Tailored cable.

In a similar solution according to DD-PS 2 18 191 Ka cable sheath and cable core, which are capacitive at the cable end are coupled together, monitored at the beginning of the cable. A however, such capacitive coupling also causes one Transmission of interference, which is an application in the PCB monitoring is in the way.

From DE 41 13 606 01 it is known for testing and lukewarm provide monitoring of (flat) printed circuit boards to apply additional conductor track to this, the thinner than the functional conductor tracks is formed in these  to feed in a signal at an entry point and at ei a read-back point of one containing the thinner conductor Control loop the picked up signal with the fed to compare.

If the thin conductor line shows - especially due to inten sive or extensive etching or mechanical damage gung - an error, the removed one deviates from the one fed off signal, and this fact is called negative Test result regarding the functional safety of the Lei used as a whole.

This solution is not for through-hole testing areas in multilayers.

The invention is therefore based on the object To create arrangement that is simple and quick Functional check of vias at both Manufacturing as well as the operational monitoring of Mehrla connections possible.

This task is accomplished by an arrangement with the features of claim 1 solved.

Expedient configurations result from the Unteran sayings.

The invention is based on the knowledge that when the special interconnect levels of the multilayer circuit Test rings with reduced dimensions applied and connected with test tracks to control loops  into which a signal is input at an entry point feeds and from which at a read-back point there standing signal is removed and with the injected Si gnal is compared, a quality test of the multilayer Board after drilling and through-hole steps as well An ongoing operational control is possible because Posi tion shifts of the individual layers against each other or of sets of holes opposite the board as well as Korro processes first in the areas of the test ring with the reduced dimensions as an impermissible cross cut or interruptions and these differ in the control loop injected from the read signal manifest who the.

If the diminished geometric dimension changes in radia ler and / or axial direction of the borehole extends surrounded by the ring, errors in a geo metric inaccuracy of attaching the mechanical Bore in every radial direction with the same sensitivity sensibility, especially when the geometric Ab measurement of one in its target position Borehole around this a substantially constant Has value. The arbitrary reduction in geometri dimensions can also result in a reduction in Material thickness of the residual ring exist, which increases next secure contacting is effected, but sol che time-dependent impairments, which a Ver cause a reduction in the coating thickness before they correspond to any remaining rings accordingly diminished geometric dimensions.  

To accomplish the signal comparison, a circuit arrangement for control loop monitoring is used, which consists of a resistance measuring device (ohmmeter) or at least one driver and at least one receiving stage and an evaluation circuit with device for outputting an error signal if the measurement signal does not match the test signal
The most important aspect of the idea of the invention with regard to the concrete choice of the geometrical dimension that is chosen smaller for the test ring (s) than for the other ("functional") ring rings is that the ring ring in the Control loop has a smaller diameter than the rest of the rings on the multilayer circuit board.

Especially for quality control with regard to etching processes in the manufacture of the printed circuit board and for the monitoring of corrosion processes in operation it may also be appropriate that the ring in the Control loop has a smaller thickness than that remaining rings on the multilayer circuit board.

Another preferred embodiment is that the control loop in every level it touches Multi-layer circuit board a ring with a ge smaller geometric dimension than the rest of the rings having.

Alternatively, it is also possible to only in certain levels that are particularly prone to errors (with regard to  Signs of corrosion, for example on the outer layers) To provide rings.

For more differentiated, about "Defect / non-defective" statements a test is particularly suitable design, between different levels of Multi-layer circuit board formed several control loops are such that one is fed in at a certain level test signal with different levels taken measurement signals can be compared.

The same purpose is also served by a configuration in which various control loops are formed, each of which comprises residual rings of a dimension selected in a predetermined gradation from the other control loops. For example, a control loop with 1 to 0.1 mm under the standard directional diameter lying annular ring diameter, a loop with a loop 2 may be formed with 3 mm to 0.3 reduced diam etc. ser ser 0.2 in reduced Restringdurchmes. The determination of which of the control loops are interrupted then enables a statement to be made about the size of the offset of the levels.

An arrangement and connection is particularly advantageous of test rings at the different levels of the Mul tilayers, which is initially a quick and easy statement enables whether there is a defect at all, and the at In the event of a defect, then locate it leaves.

In the normal case, the invention is preferably carried out in this way that all levels of the multilayer circuit board  of at least one control loop with one or more other test soldering eye (s) recorded in the corresponding plane become.

In special cases, however, it can also be enough, just by the way agreed levels - such as the outer layers of the overall structure and / or those of the intermediate laminates with test pads to be provided and included in control loops.

For the sake of simplification and therefore cheaper Realization of the arrangement lends itself to the scarf control loop monitoring overall on one Form the level of the multilayer circuit board and into each Control loop at least two vias Include areas.

But it is also possible that every control loop at least least with one associated driver and one assigned listening reception level is connected.

Another embodiment, which is particularly advantageous may be imprisoned if to be monitored by means of a the multilayer circuit board to be realized multilayer switching according to customer specifications anyway manufactured circuits, consists in that the associated with at least one control loop Circuit for control loop monitoring in an inte free function circuit on the multilayer circuit board is included.

Other features and advantages of the invention ben from the following explanation of exec  tion examples based on the figures. Zei from the figures gene:

Fig. 1 shows the basic circuit diagram of an embodiment of the invention,

Fig. 2 is a schematic diagram of the structure of a multilayer printed circuit board in cross-section,

Fig. 3 (a) and (b) are schematic diagrams for Verdeut the problem of misalignment between the feedthrough holes and conductor track trains lichung multilayer circuit board in egg ner,

Fig. 4 (a) to (c) are schematic cross-sectional representations of the feedthrough areas of multi-layer printed circuit boards according to embodiments of the invention, and

Fig. 5 is a perspective sketch of a multilayer circuit with embodiments of the invention.

In Fig. 1, the circuit arrangement for control loop fen monitoring for a multi-layer circuit board 1 with a control loop shown in FIG. 5 is shown.

A test signal T is applied via a driver 8 to a feed point 9 and passes through a control loop 7 , 7 'of the multilayer circuit board 1 as a measurement signal M to a read-back point 10 .

The readback point 10 is connected to the input of a receiving stage 11 and via a resistor R to the supply voltage Uc, and the outputs of the driver 8 and the receiving stage 11 are connected to an evaluation circuit 12 . This circuit arrangement is located on egg ner of the two outer levels 1 a, 1 b of the circuit board 1 .

In (not shown in Fig. 3 modifications), the read-back point is connected to the feed-in point of a further control loop, and its read-back point is connected to the reception stage, or each control loop is assigned its own driver and reception stage.

A DC or AC current is used as the test signal T. signal or a direct current signal with superimposed altern selstrom signal used.

In the case of a direct current signal feed, the control loop should be designed as a ground conductor. At low level at the feed point 9 , the level at the readback point 10 can be kept at a defined level by the resistor R to the supply voltage U _c = +5 V if the control loop is interrupted as a result of the ring being exceeded by the diameter of the test predetermined - maximum allowable misalignment between the holes and the interconnects.

In a production control or a goods receipt control high level is then measured at the read-back point 10 , and the evaluation circuit 12 detects an interruption of the control loop 7 (or 7 ' ) and outputs an error signal F.

In a modification, it can be fed into a direct current with superimposed AC signal or for a change current feed, preferably to rectangular pulses low low frequency.

If a negative potential (different polarity) is chosen or a level between low and high potential (e.g. from 2 V), deviations from this level can occur can be considered as errors.

An AC signal can also be superimposed on this level to - for example, in adaptation to different species fika of the function realized in the multi-layer circuit circuits - different polarities of the high level produce.

A schematic diagram of the control loop 7 , each with two on the top and the bottom 1 a, 1 b of the circuit board 1 arranged residual rings 4 a, 4 a ', 4 b, 4 b' reduced diameter, two copper sections 6 , 6 'on the walls of two holes 5 , 5 'and a flat conductor section 3 d on the underside 1 b in the schematic cross-sectional view of a two-layer circuit board shows

Fig. 4a.

In Fig. 4b a modification for a multilayer printed circuit board with levels 2 a to 2 d is shown, in which a tap (read back point) 10 b, 10 c and 10 d is provided on levels 2 b, 2 c and 2 d is, which is connected to the receiving circuit 11 or can be optionally connected and by a level-wise checking of the multilayer 1 and thus the localization of an error with respect to the level concerned is possible.

Here, in the case that the residual rings are generated together with the interconnects, no interconnect interruption in the via area is already possible on the top level, so that only the taps 10 b to 10 d are required for who.

If, on the other hand, the residual rings are generated with the step of copper-plating the boreholes, a misalignment between the rest of the rings and interconnects can occur at the top level 2 a, with the result of an interruption in the via area, so that an exact localization of the fault can already occur here Tap is needed, which is shown in dashed lines in the figure and designated 10 a.

In Fig. 4c is shown an arrangement by which both the fast By checking the multi-layer to the presence of an error in the range of several plated through-holes as well as its subsequent isolation, the exact determination of the interconnect plane ie with a probable defect is possible.

In Fig. 4c it can be seen in particular that residual rings, which are located in one of the levels 2 b to 2 d, are each located in a control loop, which only touches residual rings with reduced geometric dimensions, which are located in this plane.

Various control loops are provided in such a way that, on the one hand, residual rings, which are located in each of the planes, are both located in a control loop, which only touches residual rings with reduced geometric dimensions, which are located in this plane, as well within a further control loop, which comprises residual rings, which are located in a different plane (the bores located in a single plane are each accessible in FIG. 4c by adjacent plated-through holes).

On the other hand, those ring rings that are located in the other level are in turn located in a further control loop that only touches strings with reduced geometric dimensions that are located in the other level (the ring rings located in different levels are in the embodiment of FIG. 4c achievable through non-adjacent through contacts.). All control loops lead to the top managerial level, which can be reached externally by appropriate contacting, in order to feed and query control signals.

Here, the cable routing of the test arrangement extends over as many plated-through areas as the multi-layer 1 levels - four in the example shown - with the adjacent bore inner coatings 6 , 6 ′, 6 ′ on each of the levels 2 a to 2 d. 'And 6 ''' with each other via the associated rings 4 b, 4 b ', 4 c', 4 c '', 4 d '' and 4 d '''and one interconnect 3 b, 3 c, 3 d are connected.

The individual readback points are on the inner walls 6 , 6 ', 6 ''and 6 ''' of the holes 5 , 5 ', 5 ''and 5 '''.

The overall inspection of the multilayer is carried out by reading back on the inner coating 6 ''', while the defective multilayer level can be located via the remaining readback points if an error is detected.

In Fig. 5 is a multilayer 1 with a function block 8 , 11 , 12 from driver 8 , receiving circuit 11 and evaluation circuit 12 with the spatial profile of two control loops 7 and 7 'with the read points 9 and 9 ' and the read back points 10 and 10 'Shown in perspective. There is a line course 7 'with a minimum length and a course 7 is shown, in which two closely opposite edges of the multilayer 1 through contacting areas and extensive conductor lines on the individual levels were included in the control loop.

With the latter leadership of the control loop are in particular the consequences of corrosion problems close to the edge and mechanical stress on the multilayer early to prove.

In addition to the test arrangement, a circuit 14 is shown schematically between a component 13 centrally located on the multilayer and a circuit 15 arranged on the circuit board periphery with two through-contacting areas 16 , 16 '.

The invention is not based on the execution standing examples and their modification lungs limited, but it is a variety of others Versions conceivable from the solution shown also make use of it.

Claims (19)

1. Arrangement for quality control and monitoring of plated-through multilayer printed circuit boards ( 1 ), characterized in that in the multilayer printed circuit board ( 1 ) at least one control loop ( 7 , 7 ') is formed, the at least one ring ( 4 a to 4 a ''', 4 b, 4 b', 4 c ', 4 c'', 4 d'', 4 d''') with at least one opposite ring not in a control loop on the multilayer Lei terplatte reduced geometric dimension. 2. Arrangement according to claim 2, characterized ge indicates that the geometric dimension itself in the radial and / or axial direction of the borehole extends, which is surrounded by the ring. 3. Arrangement according to one of the preceding claims, characterized in that the geo metric dimension in a be in its target position be sensitive borehole ( 5 to 5 ''') around this has a substantially constant value. 4. Arrangement according to one of the preceding claims, characterized in that the control loop two in different levels ( 2 a to 2 d) extending plane sections ( 3 b to 3 d) and one between two levels ( 2 a to 2 d ) in the area of the plated-through holes ( 5 to 5 ''') extend the section ( 6 to 6 '''). 5. Arrangement according to one of the preceding claims, characterized in that the control loop ( 7 , 7 ') at an entry point ( 9 ) with egg ner driver circuit ( 8 ) as part of a circuit for control loop monitoring and at a readback point ( 10 , 10th a to 10 d) is connected to a receiving stage ( 11 ), such that a test signal (T) is fed in at the feed-in point ( 9 ) and a measuring signal (M) can be removed at the read-back point ( 10 , 10 a to 10 d) . 6. Arrangement according to claim 5, characterized in that the circuit for control loop monitoring an evaluation circuit ( 12 ) whose input is connected to outputs of the driver circuit ( 8 ) and the receiving circuit ( 11 ) with a device for outputting an error signal ( F) if there is insufficient correspondence between the measurement signal (M) and the test signal (T). 7. Arrangement according to one of the preceding claims, characterized in that the residual ring ( 4 a, 4 a '; 4 a to 4 a''', 4 b, 4 b ', 4 c', 4 c '', 4 d '', 4 d ''') in the control loop ( 7 , 7 ') has a smaller diameter than the remaining rings on the multi-layer circuit board ( 1 ). 8. Arrangement according to one of the preceding claims, characterized in that the residual ring ( 4 a, 4 a '; 4 a to 4 a''', 4 b, 4 b ', 4 c', 4 c '', 4 d '', 4 d ''') in the control loop ( 7 , 7 ') has a smaller thickness than the remaining rings on the multi-layer circuit board ( 1 ). 9. Arrangement according to one of the preceding claims, characterized in that the control loop ( 7 , 7 ') in each of its touched plane ( 2 a to 2 d) of the multilayer printed circuit board ( 1 ) has a residual ring ( 4 a, 4 a '; 4 a to 4 a''', 4 b, 4 b ', 4 c', 4 c '', 4 d '', 4 d ''') each with a smaller geometric dimension than the remaining rings on the each level ( 2 a to 2 d). 10. Arrangement according to one of the preceding claims, characterized in that between different levels ( 2 a to 2 d) of the multilayer circuit board ( 1 ) a plurality of control loops ( 7 , 7 ') are formed such that one in one of the levels ( 2 a to 2 d) test signal (T) fed in can be compared with a measurement signal (M) taken off in another plane ( 2 a to 2 d). 11. Arrangement according to one of the preceding claims, characterized in that Restrin ge, which are located in each of the levels, in a control loop, which are exclusively Remaining rings with reduced geometric dimensions stirs, which are located in this plane. 12. The arrangement according to claim 11, characterized ge indicates different control grinding are provided in such a way that on the one hand Restraining rings, which are located in one of the levels are, both in a control loop, wel che only rings with reduced geometri dimensions touched that located in this plane are, as well as within a further control loop are located, which contain residual rings, which in another levels are located. 13. Arrangement according to claim 12, characterized ge indicates that the residual rings in the other levels are located, again in a wide area control loop, which are exclusively Remaining rings with reduced geometric dimensions stirs, which are located on the other level. 14. Arrangement according to one of the preceding claims, characterized in that jedtli che levels ( 2 a to 2 d) of the multilayer printed circuit board ( 1 ) by at least one control loop ( 7 , 7 ') are detected. 15. Arrangement according to one of the preceding claims, characterized in that several control loops ( 7 , 7 ') with residual rings ( 4 a to 4 a''#, 4 b, 4 b', 4 c ', 4 c'' , 4 d '', 4 d ''') are provided within a control loop of the same, but compared to the other control loops by a predetermined amount of graduated geometric dimensions. 16. Arrangement according to one of the preceding claims, characterized in that the circuit for the control loop monitoring overall on one level ( 2 a to 2 d) of the multilayer printed circuit board ( 1 ) is ge and each control loop ( 7 , 7 ') at least two plated-through holes Areas. 17. Arrangement according to one of the preceding claims, characterized in that each control loop ( 7 , 7 ') with an associated driver ( 8 ) and an associated receiving stage ( 11 ) is connected ver. 18. Arrangement according to one of the preceding claims, characterized in that the circuit with at least one control loop ( 7 , 7 ') connected to the control loop monitoring is contained in an inte grated functional circuit on the multi-layer circuit board ( 1 ). 19. Arrangement according to one of the preceding claims, characterized in that the one feed point ( 9 ) is on a flat section of the control loop ( 7 , 7 ') and the read-back point ( 10 ) is in a via section or vice versa.