DE4315273C1 - Stuffing control signal generating circuit for signal data rate modification - uses detected count difference between write address counter and read address counter for buffer memory - Google Patents

Abstract

The circuit generates the stuffing control signals by evaluating the count difference between a write address counter (21) and a read address counter (22) for addressing a buffer memory (SP). Each counter comprises a multistage Johnson counter, their data outputs being coupled to the data inputs of a respective register (R1,R2). The count differences between the counter count values are provided by a logic circuit (LOG) coupled to the outputs of the two registers converted into stuffing control criteria (g,k). ADVANTAGE - Relatively simple circuit providing stuffing control signals for high data rates.

Description

The invention relates to a circuit arrangement according to the Preamble of claim 1.

If plesiochronous data signals become a multiplex signal too can be summarized or via a synchronous transmission direction are to be sent, the data rate is determined by a process called plugging on the data rate of the Adapted transmission path. In "Digital transmission tech nik ", Peter Kahl (Editor), R. v. Decker′s-Verlag G. Schenk, Heidelberg, Vol. 1, Chapter 1.4.4 page 9 to page 14 are the different stuffing methods for pulse code modules lation (PCM) procedure described, in which several plesio Chronic data signals each arranged in a pulse frame become. This pulse frame contains fixed bit positions, each for example, two fill bits, one fill bit and one if required Data bit or two data bits included. This procedure will referred to as positive-zero-negative plug.

The data to be transferred are first assigned with a Neten write clock signal in a buffer memory ben. The data is transmitted with an internal clock signal read out. Depending on the filling level of the buffer tank Tax criteria are obtained that meet the corresponding criteria Trigger darning processes and as darning information to the recipient be transmitted. The addressing of the buffer memory takes place via a write address counter and a read address counter with a count that corresponds to the amount of memory. The degree of filling of the memory is determined by difference between between the write address and the read address Times determined. Depending on whether he's smaller, is equal to or greater than a predetermined setpoint the control criteria for the three via a logic circuit  Darning opportunities won. In addition, the clock signal of the Read address counter and with this the output from the puf memory controlled according to requirements. Because the writing clock signal to a different frequency than the read clock signal points and is not correlated with this, there is Danger that the meter reading differences are not determined exactly become.

The invention specified in claim 1 is the problem based on a circuit arrangement with little effort Generation of stuffing control signals at high data rates give.

Advantageous embodiments of the invention are in the dependent indicated claims.

It is particularly advantageous in this invention that also in critical positions of the clock edges the meter reading and thus also the counter corresponding to the filling level of the memory level difference is falsified by at most one. Through the Intermediate storage of the counter contents in registers with the The same clock signals represent a com for the logic circuit complete clock period available for decoding. This enables light a meshed multi-stage gate arrangement, the Gat ter number can be greatly reduced.

Advantageously, only two binary stuff control signals generated, each specifying one of the three tamping processes.

The use of Johnson counters has the advantage that only the state of a flip-flop or at Johnson counters with an odd count range only the state of a flip-flop relevant for decoding changes. The meter readings are also particularly easy to do decode.  

The specified circuit arrangement can be used for Johnson counters can be expanded with any number of counts.

An embodiment of the invention is based on figures explained in more detail.

It shows

Fig. 1 is a block diagram of the inventive circuit arrangement,

Fig. 2 shows the essential for the present invention circuits,

Fig. 3 is a diagram of Stopfsteuersignale,

Fig. 4 is a Johnson counter with a timing chart

Fig. 5 shows an advantageous logic circuit and

Fig. 6 shows a logic circuit for determining the zero count difference.

The circuit arrangement in FIG. 1 shows a buffer memory SP in which data of an incoming digital signal D1 is stored with an assigned write clock signal T1. The write address AW is generated by a write address counter Z2, the data outputs of which are connected to the corresponding address inputs of the buffer memory SP. The read address AR is generated by a read address counter Z2, the outputs of which are routed to the corresponding address inputs of the buffer memory. Furthermore, the outputs of the write address counter are connected to a first register R1 and the outputs of the read address counter are connected to a second register R2. In addition, a logic circuit LOG operating as a comparison and coding circuit is provided, to which the write and read addresses are fed from the outputs of registers R1 and R2. The logic circuit determines two stuffing control signals g and k. A control device ST can interrupt a work cycle signal TS on the basis of these stuffing control signals g, k and thereby generates a read clock signal T2 which is fed to the clock input of the read address counter Z2. This also controls the output of the data signal D2. With the work clock signal TS, the counter readings are transferred to the registers R1 and R2 assigned to them. In Fig. 1 only the essential circuits relevant to the invention are shown and only the functions of the control necessary for this are explained. Circuit variants are of course possible.

Fig. 2 shows again the write address counter Z1, the associated first register R1, the read address counter Z2, the associated second register R2 and the logic circuit LOG. Only the write address counter Z1 is supplied with the write clock signal T1 associated with the arrival of the digital signal D1. The read address counter Z2 and the two registers R1 and R2, on the other hand, work with the read clock signal T2 and the work clock signal TS. The data outputs s1, si. . . sN of the write address counter Z1 are connected to data inputs of the first register R1. The data indicating the counter reading Z1 are transferred to the first register R1 in parallel with the read clock signal T2. In the same way, the data outputs are l1. . . left . . IN of the read address counter Z2 connected to data inputs of the second register R2. The data outputs S1. . . SN and L1. . . LN of both registers R1 and R2 including their inverting outputs. . . respectively. . . . are connected to the logic circuit LOG, which has two outputs G and K, at which the stuffing control signals g and k are emitted.

In the diagram of FIG. 3, the logical states of the stuffing control signals g and k are a function of the difference in the counter status ZD between the write counter status ZS1 and the read counter status ZS2 of the counters Z1 and Z2. In addition, a further criterion ZD0, which is required anyway, is shown, which is generated by a logic circuit shown in FIG. 6. This criterion only changes its logic state when the count difference is zero. The justification control criteria and the counter difference ZD0 determine the type of justification, where "+" stands for positive, "-" for negative and "0" for zero.

A Johnson counter is shown in FIG . It corresponds to a cross-fed feedback register, whose JP flip-flops are clocked by a clock signal T. The associated time diagram and the truth table illustrate the function. The designation of the outputs s1 to s4 corresponds to that of the counter Z1. These counters are particularly suitable for high clock rates since they do not require any gate circuits. The individual meter readings are also easy to decode.

It is also possible to use Johnson counters for a range of counters from 2N-1 to use. Then the logic circuit corresponds to modify accordingly.

In Fig. 5, an embodiment of the logic circuit is shown. This corresponds to a meshed switching network. All combinations of Q and Q outputs S1, L1,. . . ,. . . , SN, LN of the first flip-flops of both registers R1 and R2 are combined via AND gates G1 to G4. The outputs S2. . . SN, L2. . . LN; . . . ,. . . the other equivalent flip-flops via registers AND gates UND11 to UND1N, UND21 to UND2N. . . . . summarized to UND41 to UND4N. The same designations are used for the inputs and outputs and their logical variables in the following considerations.

The outputs of these AND gates UND11. . . UND1N to UND41. . . UND4N - more precisely their logical variable - are each over a NOR gate NOR1 to NOR4 linked together. The complete AND-NOR circuits are labeled G5 to G8 net. According to the number "N" of flip-flops of the Johnson The number of AND gates U11 to U4N is measured, the number of NOR gates remains the same.  

In a further stage of the network, the outputs U1 to U4 the AND gates UND1 to UND4 and that of the outputs  . . . the NOR gates NOR1 to NOR4 (or G5 ... G8) via four further AND gates UN11 to UN14 or UN21 to UN24 with linked together. The outputs of these AND gates UN11 to UN14 and UN21 to UN24 are each again identified by a OR function - here the OR gates OR1 or OR2 - with each other the linked. These AND-OR circuits are with G9 or Designated G10. At the output of the G of the further OR gate ters OR1 the stuffing control signal g is emitted and to the Output of the further OR gate OR2 the stuffing control signal k. Of course, all d'Morganschen also deliver Transforms the logic circuit the same result. Likewise, instead of inverting or non-inverting Outputs of the two counters Z1, Z2 also AND gates AND11. . . UND4N and AND gate G1. . . G4 with one or two inverting inputs are provided.

The logical links are in the claims specified.

The logic circuit is for any number of N flip comprehensive Johnson counters expandable. It increases only the number of AND gates UND1i to UND4i N each and the number of inputs of the NOR gates NOR1. . . NOR4.

In Fig. 6 is a logic circuit LS for generating the logical criterion count difference of zero is shown, there is at the tie ZD0 between two counter states. It contains N exclusive NOR (OR) operations EX1. . . EXN, the outputs of which are connected to inputs of an AND (OR) gate AND. If the equivalent outputs of both counters Z1 and Z2 (or registers R1 and R2) have the same logic states, ie they show the same counter readings, then log 1 (or a "log . 0 "for inversion).

The logic circuits can correspond to the transformations by de′Morgan (TTL cookbook, p. 85) including the "positive" and "negative" logic (TTL cookbook, p. 86) be changed.

Claims (4)

1. Circuit arrangement for generating stuffing control signals (g, k) by evaluating counter reading differences (ZD = ZS1-ZS2; ZS1 / ZS2 = 0, 1...;... 2N-1) of a write address counter (Z1) and a read address counter (Z2); used for addressing a buffer memory (SP), characterized in that
that the write address counter (Z1) and the read address counter (Z2) are designed as N-stage Johnson counters,
that the data outputs (s1, s2... sN) of the write address counter (Z1) are connected to data inputs of a first register (R1) and data outputs (l1, l2... lN) of the read address counter (Z2) are connected to data inputs of a second Register (R2) are connected
that the clock input of the write address counter (Z1) is supplied with a write clock signal (T1) belonging to the data to be stored,
that the clock inputs of the read address counter (Z2) and the first and second registers (R1, R2) are supplied with a read clock signal (T2) or working clock signal (TS) belonging to the output data (D2),
that at least N data outputs (S1... Si... SN; L1... Li... LN) of the first and second registers (R1, R2) are connected to inputs of a combinatorial logic circuit (LOG) and
that the following logical assignment exists between meter reading differences ZD of the two meters (Z2, Z1) and the stuffing control signals g, k (or their inverted signals):
g = 1 (0) for 0 = ZD N, otherwise 0 (1) and
k = 1 (0) for 0 ZD N, otherwise 0 (1). 2. Circuit arrangement according to claim 1, characterized in that
that the combinatorial logic circuit (LOG) has four AND gates (G1 to G4) with outputs U1 to U4, with the outputs S1,. . . SN, the first register (R1) and outputs L1,. . . Ln, of the second register (R2) are linked as follows: that the logic circuit has four AND-NOR gates (G5 to G8) with the outputs (to), which are linked to the register outputs Si, Li, as follows: that the logic circuit contains two AND-OR gates (G9 and G10) with outputs G and K, which with the outputs (U1 to U4) of the AND gates (G1 to G4) and the outputs (to) of the AND-NOR Gates (G5 to G8) are linked in the following way: 3. A circuit arrangement according to claim 1, characterized in that a logic circuit (LS) is provided, in the tie ZD0 between the counter readings of the registers (R1) and (R2) by an AND operation of the antivalences / equivalences (EXCLUSIVE-NOR (OR links) between equivalent outputs S1, L1. . . SN, LN of registers (R1) and (R2) is detected. 4. Circuit arrangement according to one of the preceding claims che, characterized, that it includes de'Morgan transformations.