DE4313490C1 - Costas loop for demodulation of phase shift keying - Google Patents

Abstract

The invention relates to a Costas loop (for demodulation of phase shift keying) comprising the two main modules, an I/O demodulator for synchronous demodulation of the input signal into an in-phase and a quadrature-phase component and a control voltage system to generate a modulation-independent control voltage to correct the voltage-controlled oscillator (VCO). This is characterised in that the control voltage system comprises a four-quadrant multiplier, a squaring element and a loop filter.

Description

The invention relates to a Costas loop Demodulation of phase shift keying with those in the preamble of claim 1 specified features.

Such Costas loops are used to recover the Carrier frequency from a carrier frequency signal Synchronous demodulation of the output signal in an in-phase and in a quadrature phase component and have Control voltage network for generating a modulation-independent Control voltage for tracking a voltage controlled oscillator. This will be so long readjusted until the oscillator frequency in frequency and Phase coincides with the carrier frequency.

In the known versions of the Costas loop for QPSK Demodulation is used in the practical embodiments basically differentiated between the Costas loop conventional type, in which one uses four synchronous detectors by 45 ° phase-shifted reference carrier signal and the control voltage network consisting of three multipliers and the loop filter exists; a Costas loop after the Cross-over principle, consisting of I / Q demodulator and Control voltage network with two multipliers, two Delimiters, an adder and a loop filter and the Costas loop, which consists of a maximum-a-posterior Algorithm derived from I / Q demodulator and Control voltage network with two squares, two Multipliers, an adder and a loop filter exists (M. K. Simon, "Optimum Receiver Structures for Phase- Multiplexed Modulations ", IEEE Transactions on Communications, vol. COM-26, 6/78, pp. 865-872).  

A tutorial review entitled "Carrier and Bit Synchronization in Data Communication" is published in the specialist journal "IEEE Transactions on Communications", 1980, No. 8, pages 1107 to 1121. From this publication, Costas loops are known from FIGS. 2 (a) and 2 (b), which are suitable for producing a coherent carrier for BPSK demodulation, a quadrupler being used instead of the squarer in front of the mixer in the first embodiment can be used to create a coherent carrier for QPSK demodulation. To implement a BPSK demodulator, it is necessary to divide the frequency of the coherent carrier and mix it with the input signal. The embodiment according to Fig. 2 (b) is not suitable for a QPSK demodulation.

Disadvantages of these embodiments of the Costas loop are on the one hand, the high circuit complexity due to the large number of components required and the other Problems of amplitude and transit time differences, which can arise as a result of the branched structures of the electrical circuits and the different Transfer functions of RF mixers, limiters and Multipliers.

The invention has for its object a minimization the circuitry involved in QPSK demodulation achieve and through a suitable circuit structure for it to ensure that unequal transfer functions of the individual components no longer have a negative impact on them So there is no need to compensate specifically.

The object is achieved by the invention according to the Claim 1 specified technical teaching.

The achievable with the invention, which for the If QPSK demodulation applies, that are available after the I / Q demodulator orthogonal baseband signals, which are in the in-phase channel and are in the quadrature phase channel by means of the Four quadrant multiplexers are multiplied together, and that the product thereafter in the straight-ahead process is processed by squaring and then is filtered.

The two nonlinearities multiplier and squarer are required (with QPSK) to eliminate the modulation content in the readjustment voltage. Since the signal flow only takes place on one line after the multiplier, amplitude and transit time differences can no longer appear. Amplitude imbalance due to different transmission _factors k _m1 and k _{m2 of} the HF mixer also no longer play a role, since these are multiplied with one another in the four-quadrant multiplier.

An embodiment of the invention, in which the Option of BPSK demodulation is provided in the drawing shown. It shows

Fig. 1 is a block diagram of the Costas loop with modified control voltage generator, including the appropriate physical quantities,

Fig. 2, the modulation contents of a (t) and b (t),

Fig. 3 shows the error term u _d (t) and E [u _d (t)],

Fig. 4 shows the offset and control terms u _o (t) and u _c (t) and E [u _o (t)] and E [u _c (t)].

The circuit arrangement according to Fig. 1 consists essentially of a divider, preferably a 0 ° / 3dB splitter to whose input the signal is applied. Furthermore, a first mixer 3 and a second mixer 3 'are connected to the divider 1 . The mixers 3 and 3 'are connected in each case arm filters 4 in the output signal path of the demodulator. Between the two mixers 3 and 3 'a further 0 ° / 90 ° divider or phase shifter is interposed, the input of which is connected to a voltage-controlled oscillator 5 . The in-phase signal is fed to the first mixer 3 , the signal rotated by 90 ° to the mixer 3 '. The specified circuit groups belong to the I / Q demodulator. The voltage controlled oscillator 5 is controlled by a control voltage network consisting of a multiplier 8 , the two inputs of which are connected to the outputs of the arm filters 4 and 4 'or are connected to the outputs A', B '. The multiplier is followed by a changeover switch 9 , via which either a squarer 7 can optionally be switched on or a shunt to the squarer can be switched on. The squarer output and the shunt are connected to a loop filter input 6 of the control voltage network, the output of which is connected to the voltage-controlled oscillator 5 and the voltage of which adjusts the VCO 5 .

The invention is explained with the aid of the mathematical description in the time domain for the case of QPSK demodulation - in the case of the BPSK the circuit corresponds to the known Costas loop for this case (I. Frigyes et al., Digital Microwave Transmission, Akad´miai Kiado , Budapest, 1989, p. 299) - with reference to the sizes shown in the block diagram. The constants k _m1 . . . k _m3 and K _s have the dimension 1 / V. The QPSK-modulated input signal is in the form

before, with a (t) and b (t) as the modulation content (dimensionless, with the amplitudes A = B = 1) and ω _s as the carrier angular frequency. You can write for the orthogonal reference signals

u _ri (t) = 2Û _r cos [ω _s t + Φ (t)] (2.1)

and

u _rq (t) = -2Û _r sin [ω _s t + Φ (t)] (2.2)

where phase Φ (t) consists of a component caused by the frequency difference between the signal and VCO Δω = ω _s -ω _r and the reference carrier phase Φ _r : Φ (t) = Φ _r -Δωt. The signals are then in-phase and quadrature phase components - assuming that the arm filters ( 4 , 4 ') are used exclusively for the suppression of spectral components with 2ω _s

u _i (t) = k _m1 Û _s Û _r [a (t) cos Φ (t) + b (t) sin Φ (t)] (3.1)

and

u _q (t) = k _m2 Û _s Û _r [b (t) cos Φ (t) - a (t) sin Φ (t)] (3.2)

to disposal.  

The output of the multiplier (8) thus delivers

u _i (t) u _q (t) = k₁ [a (t) b (t) cos 2Φ (t) + ½ {b² (t) - a² (t)} sin 2Φ (t)] (4)

with k₁ = k _m1 k _m2 k _m3 Û _s ²Û _r ². Then lies at the exit of the squarer

[u _i (t) u _q (t)] ² = k₁²k _s [u _o (t) + u _c (t) cos 4Φ (t) + u _d (t) sin 4Φ (t)] (5)

The substitutions in Eq. (5) are composed as follows:

u _o (t) = ¼ a² (t) b² (t) + ⅛ a⁴ (t) + ⅛ b⁴ (t) (offset term),

u _c (t) = ¾ a² (t) b² (t) - ⅛ a⁴ (t) - ⅛ b⁴ (t) (control term),

u _d (t) = ½ a (t) b (t) [b² (t) - a² (t)] (disturbance term).

At this point it can already be seen that for the case of rectangular modulation functions {ie for a (t) ∈ ± 1 and b (t) ∈ ± 1} in Eq. (5) the influence of the modulation is eliminated, since the terms u _o (t) = ½, u _c (t) = ½ and u _d (t) = 0 then apply. In practice, however, the modulation contents are band-limited and scrambling ensures that the values of the successive bits are changed as often as possible. Therefore, after the squarer (7), the loop filter (6) is required, which for the terms u _o (t), u _c (t) and u _d (t) act as an integrator, _i.e. their expected values E are generated. With an ideal integrator (with an infinitely long integration time) the transitions would

u _o (t) = <E [u _o (t)] = const,

u _c (t) = <E [u _c (t)] = const,

u _d (t) = <E [u _d (t)] = 0

be carried out. In practice, the integration time cannot be made arbitrarily long and thus the filter cut-off frequency cannot be made arbitrarily small in order to enable an acquisition process for Δω ≠ 0. The loop filter (6) must be dimensioned in such a way that sufficient smoothing of the offset and control voltages u _o (t) and u _c (t) is ensured and the interference voltage u _d (t) is sufficiently small, but is still a catch operation for Δω ≠ 0 can take place. In general, the following applies: the weaker the band limitation of the modulation functions, the shorter the integration time, the larger the filter bandwidth and the capture range.

The process of averaging through the loop filter (6) is shown in Fig. 3 for u _d (t) and in Fig. 4 for u _o (t) and u _c (t). The corresponding modulation functions a (t) and b (t) (also called dibit sequences) in FIG. 2 are to be considered as examples. The band limitation is implemented by a 2nd order Bessel filter, which roughly corresponds to the cos² formation with rolloff factor r = 0.5 which is often used in practice. A simple RC low-pass filter with a selected time constant of τ = 2T _db serves as the loop filter (in the example, the dibit duration is T _db = 97 ns). The settling processes shown run from 0 to 1.2 µs. The amounts of the expected values E [u _o (t)] and E [u _c (t)] are around ¼ for the band limitation of a (t) and b (t). The pictures should serve to illustrate the integration effect!

The acquisition process is briefly explained qualitatively. Signal and reference frequency should be far enough apart at time t Zeit = 0, ie Δω (0) should be so large that the terms with cos Φ (t) and sin Φ (t) are suppressed by the loop filter. Then only the filtered offset term E [u _o (0)] is effective and the VCO tracking voltage is

u _e (0) = k₁²k _s E [u _o (0)] (6)

therefore the reference frequency changes

Δω _r = k _o k₁²k _s E [u _o (0)] (7)

with the VCO constant k _o in rad · s ^-1 · V ^-1 . If this change in reference frequency now leads to the fact that the VCO frequency for t <0 already comes close to the signal frequency ω _s , then Δω becomes smaller until finally the frequency catch at Δω = 0 is reached. Then applies to the subsequent phase locking

u _e (Δω = 0) = k₁²k _s {E [u _o ] + E [u _c ] cos 4Φ} (8)

from which stable states at Φ = n · π / 2 (n = 0, 1, 2, 3) are derived (provided that the expected values for the terms are reproduced by the loop filter). The VCO freewheeling frequency must therefore be determined so that it is increased by the amount Δω _r according to Eq. (7) lies below the signal frequency in order to be able to safely initiate an acquisition process.

As with the known variants of the Costas loop by the π / 2 periodicity of the control voltage (as a function of Φ) a fourfold uncertainty regarding the generated Reference carrier phase Φ, so that the demodulated bit streams a ′ (t) and b ′ (t) either

• - correspond to the modulation functions a (t) and b (t) or
• - are interchanged or
• - are inverted or
• - are inverted and interchanged.

In practice, this indeterminacy is Coding eliminated.

Claims (5)

1. Costas loop, consisting of two main groups, an I / Q demodulator for synchronous demodulation of the input signal into an in-phase and a quadrature-phase component, and a control voltage network for generating a modulation-dependent control voltage for tracking the voltage-controlled oscillator (VCO ), characterized in that the control voltage network consists of a four quadrant multiplier ( 8 ), a square ( 7 ) and a loop filter ( 6 ). 2. Costas loop according to claim 1, characterized in that the four-quadrant multiplier ( 8 ) multiplies the two orthogonal output voltages of the I / Q demodulator directly with one another, that the resultant signal in the case of a four-phase shift keying (QPSK) via a switch ( 9 ) Squarer ( 7 ) is supplied, the output signal of which then reaches the loop filter ( 6 ) and finally, after low-pass filtering, represents the tracking voltage for the VCO ( 5 ) for QPSK demodulation. 3. Costas loop according to claim 2, characterized in that in a two-phase shift keying (BPSK) via the switch ( 9 ) a shunt to the square ( 7 ) is switched on and the result signal is fed directly to the loop filter ( 6 ). 4. Costas loop according to one of the preceding claims, characterized in that between the four-quadrant multiplier ( 8 ) and the loop filter ( 6 ) a square ( 7 ) is interposed when receiving QPSK signals. 5. Costas loop according to claim 2 or 3, characterized in that the output of the four-quadrant multiplier ( 8 ) is followed by a switch ( 9 ) which, operated manually or automatically, connects the output to the squarer in the case of four-phase shift keying of the demodulated signal and in the event of detection of the two-phase shift keying or by appropriate manual switching of this operating mode, shorts the squaring device ( 7 ), and that the output signal is fed to the respective loop filter, from the output of which the readjustment voltage for the voltage-controlled oscillator ( 5 ) can be tapped.