DE4007895A1 - METHOD FOR REDUCING HOT ELECTRON DEGRADATION IN SEMICONDUCTOR COMPONENTS - Google Patents

Abstract

A method of reducing the degradation effects associated with avalanche injection or tunnelling of hot-electrons in a field-effect semiconductor device is disclosed and includes covering the active regions of the semiconductor device with a protective titanium based barrier layer (19) which is deposited directly underneath the ordinary metalization layers (20) used for connecting the devices to bit and word lines within an array. Inclusion of the titanium based barrier layer in a flash memory device results in a substantial improvement in the erasetime push-out and reduces excess charge loss normally associated with hot-electron devices. The titanium based layer can be of titanium, titanium nitride, and titanium tungsten. <IMAGE>

Description

The invention relates to a method of manufacture electrically programmable and electrically erasable memory cells and in particular on reducing degradation or degradation effects of hot electrons (hot electron degradation) in such cells.

Hot-electron induced n-channel MOSFET degradation sets in Problem with both present and future VLSI circuits, because of the ever increasing electrical channel field in scale components. Degra dations effects of hot carriers particularly harmful to the reliability of those components elements caused by electrical charge transfer mechanisms, such as avalanche injection, canal injection, Fowler-Nordheim-Tun neleffekt, hot electron injection from the substrate etc. work Included in this component category are electrical programmable read-only memory (EPROMS) and elec Programmable and electrically erasable memory (BEPROM’s).

Flash memories (e.g. EEPROM's) are against degradation effects particularly sensitive, precisely because it is a considerable number of hot electrons exist in each Cell during electrical programming and erasing be generated. In these flash memories the performance of hot electrons are driven to extreme limits. Wuh during the flash memory cycles (i.e. with repeated program mieren and delete the component) is, for example considerable number of hot electrons in the substrate captured within the insulating gate oxide layer, which separates the drain from the floating gate. The bigger the Number of cycles that a flash memory device is subjected, the greater the number of those in the gate oxide captured charge carriers.

Degradation effects of hot electrons are stored in flash memory  observed in two ways. That is particularly clear Increase the deletion / programming times of a given Storage arrangement beyond normal limits. This Phenomenon is often called "erase time / program time push-out" designated. This means that repeated cyclic Operation of the components an increasingly large delete / pro gram time can be assigned to each successive cycle must ensure that the overall arrangement is full is constantly being loaded or unloaded.

The second type of degradation effects is expressed in one Flash memory device in the form of an excess - ("obvious Lichen ") loss of charge that the storage elements unreliable sig does. Even if the component was originally on a "obviously" correct level has been programmed this degradation effect means that the programming level with time below the limits for a reliable Opera tion can drop. This "obvious" loss of charge is followed by a shift in the steepness of the components extensive programming / deletion cycles.

Although the exact mechanism of component degradation is still Not known, many studies have shown that he is on a hydrogen-related boundary layer state generation could be fed. This theory assumes that hydrogen during various treatment steps, including the last tempering step, included in the component structure becomes. A hydrogen source is the hydrogen-rich Passi junction layer, which is typically a form of oxide or Contains nitride (e.g. the commonly used oxide nitride).

To improve the stability of the hot electrons in MOS Various solutions have been proposed for components. So For example, a group of researchers has the drain dotie  profile by grading the drain zone or using light doping levels for the purpose of reducing the electrical channel field strength successfully modified. But even when using these field reducing structures the degradation induced by hot electrons continues stand.

In an article in IEDM 88, page 22ff, entitled "Ver Improvement of stability against hot charge carrier degra dation by hydrogen blocking P-SiO "by S. Yoshida u. a., was the use of a plasma silicon oxide as Means to improve the hot-electron problem featured beat. The authors assumed that a Blocking effect against hydrogen by capturing what seratome to free or loose bonds, such as those in the plasma silicon oxide layer are present, can be caused. The plasma silicon oxide has an excellent ability to Capture and block hydrogen shown.

An alternative method of performing a final tempe tion in a nitrogen atmosphere instead of a normal one Hydrogen atmosphere is in an article by F-C. Hsu u. a. with the designation "Effective final tempering at hot electron-in Reduced MOSFET Degradation ", in IEEE Electron Device Let ters, volume EDL-6, No. 7, July 1985. This arti Kel describes that the hydrogen content in certain components ment with the help of a final tempering in a nitrogen atmosphere can be reduced. Therefore the hot electron degradation to a negligible level be reduced. A low hydrogen content results a lower degradation such as Hsu u. a. to report. These Results are decisive for the hydrogen model Hot electron induced device degradation.  

Another method using a long nitrogen annealing step is described in an article by Shuo-Tung Chang, inter alia, entitled "Reduced Oxide Charge Capture in MOS Devices Manufactured by a Titanium Salicide Process, Improved Hot Electron Reliability own and have submicron dimensions ", IEEE Electron Devices Letters, Volume 9 , No. 5, May 1988. Nitrogen temperature is described in connection with a titanium salicide (self-aligning silicide) process, which is a new technique for reducing the Source-drain resistor in silicon gate devices. The titanium silicide forms the gate electrode of the component. The authors found that titanium sputtering can cause radiation damage to the silicon oxide interface by creating interface states, thereby reducing transistor performance. Hydrogen annealing was typically carried out to remove this radiation damage. The authors discovered that the use of nitrogen instead of hydrogen for annealing results in lower hot electron degradation.

Even using some of the methods discussed above the hot electron voltage in flash memories remains low stes problem- especially when flash memory in user with extended cycles. Doing so they have the ability to perform multiple cycle surgery without one Extinguishing time push-out or excessive charge trapping in the Endure oxide layer.

As will be seen, the invention provides a method for Manufacture of flash memory devices available at which is essentially a barrier layer made of titanium with normal metallization layers becomes. This titanium barrier layer is not inadvertently  converted into silicide and actually forms part of the connecting metallization material. The inclusion of this Barrier layer causes in the passivation layer containing hydrogen with that in the gate oxide zone Storage elements occurring continuous charge transfer interaction occurs. Using the Invention According to the procedure, the push-out of deletion times is neglected casual and the reliability of the flash memory elements considerably increased.

A method for reducing the hot elec is described tron-induced degradation effects in field effect semiconductors elements. According to the invention, a protective metallic Barrier layer over at least one of the active areas of the semiconductor element before the deposit is deposited down layer. The metallic barriers Layer should be made of a material that has an affinity possesses hydrogen, the equivalent of which is harmful for hot-electron components. With one preferred Th embodiment is a titanium layer with a thickness deposited by 150 nm, and this layer has edges that with those of the bit line in a memory array forming aluminum metallization layer coincide. The Titanium barrier layer contacts the drain zone of the Bauele elements, which creates an electrical connection. By using the method according to the invention the extinguishing time push-out and excess charge loss effects in Flash memory devices significantly reduced.

In the following the invention based on one in the drawing illustrated embodiment explained in more detail. In the Show drawing:

Figure 1 is a sectional view through a flash EEPROM component, which is made with a metal barrier layer according to the preferred embodiment of the invention.

FIG. 2 is a top view of the flash EEPROM device shown in FIG. 1, FIG. 2 illustrating the relationship of the barrier metal layer to the aluminum metallization layer in the preferred embodiment of the invention;

Fig. 3A, the border and Spannungsschwellwertverschiebungen for 5000 cycle units, followed by a Tem perungsschritt at 250 ° C for 48 hours; the data for Figure 3A was obtained on a device that was fabricated without the barrier metal layer;

Fig. 3B in comparison the limit and voltage threshold shifts for 5000 cycle units, followed by a 250 ° C annealing step for 48 hours on components that were produced using the inventive method.

Fig. 4A, the deleting time push-out in seconds for a pe Grup by without a barrier metal layer hergestell th components; and

Fig. 4B in comparison, the extinguishing time push-out for a group of components manufactured according to the invention.

An improved method of manufacture is described of field effect components with the help of hot electron-in reduced degradation effects can be reduced. In the  following description are numerous special details such as thicknesses, compositions, etc. To deepen understanding of the present invention. It is however, it will be clear to those skilled in the art that these specific items not for the implementation of the present invention are crucial. In other cases, known treatments are used steps not shown in detail to the invention not burdened with unnecessary details.

The memory cell according to the invention is using the Metal oxide semiconductor (MOS) technology manufactured. The ever Weil used special processing is for the invention not critical, since the invention is easy to manufacture process for components can be adapted, the hot electron de subject to gradation effects. In the preferred embodiment Example of the method according to the invention is in Verbin with a method for producing a flash memory component (i.e. EEPROM) or a memory field on hot electron injection or tunneling through Carriers between the substrate and a floating gate elec trode is based.

As mentioned above, there is repeated cyclic reloading from flash memories to charge losses from the floating gate and a corresponding degradation in the component line stung. It is believed that this phenomenon occurs in part the introduction of hydrogen into the active zones of the field effect component goes back. The presence of water fabric reinforces the interface state generation (interface state generation) and causes component degradation. Although most flash memory elements are usually like this are made that the active and channel zones of one Aluminum metallization layer can be covered despite the hydrogen atom under this metallization layer  the open spaces between the metal lines diffuse.

Referring now to Fig. 1, there is shown a flash memory cell made using the method of the preferred example.

In short, memory cells according to the preferred example are produced on a p-type silicon substrate 13 . A crystal orientation of <100 <is used with a relatively lightly doped substrate (38 to 36 ohm-cm). Field oxide zones (isolation zones) 15 are first defined using a silicon nitride masking layer, whereupon field oxide is grown to a thickness of approximately 750 nm.

After the formation of the field oxide areas, high-quality tunel oxide 24 will thermally grow above the channel zone of the substrate. The thickness of the tunnel zone oxide layer is approximately 10 nm. Thereafter, a phosphorus-doped polycrystalline silicon layer 16 is deposited and etched in a pattern of parallel strips, which subsequently form the floating gate electrodes for each of the memory cells. After thermal growth of a dielectric layer 22 over layer 16 , a second layer of polysilicon 17 is deposited and etched in parallel strips which are generally perpendicular to those of layer 16 . The second layer 17 defines the control gate for the memory element and serves as a mask for etching the layer 16 underneath. Layer 16 forms the floating gate of the device. A control gate device 17 extends across the active channel zone 12 of the cell and extends beyond the tunnel zone to the next cell, thereby forming a word line in the memory array.

The source and drain zones for the cells are formed according to the definition of the poly-2 layer 17 . First, an arsenic implant is used to form a relatively thin source-drain zone. In the preferred example, arsenic implementation takes place at 60 keV to a concentration level of 4 × 10 ¹⁵ atoms / cm ² . The source zones receive an additional phosphorus implantation at 60 keV to a concentration of 6 × 10 ¹⁴ atoms / cm ² . This results in a relatively deep phosphor-source transition, since phosphorus diffuses easily into the silicon. This implant causes the source side to have a steeper and more gradual dopant concentration gradient than the drain side. Alternatively, these zones can be formed by ordinary diffusion steps. As shown in Fig. 1, a deeper implantation in the source zone 11 is used to reduce the substrate current during electrical erasure. (Zone 11 represents a common zone within the flash memory field).

After the formation of the source and drain zones, a thermal oxide layer 23 is grown on the source / drain and poly-gate surfaces. A CVD dielectric layer 18 is then deposited on top of the thermal oxide layer to level the device.

In order to open the drain contact, the component is masked and etched until a silicon region is exposed directly above the drain zone. This will become the drain contact zone 14 according to FIG. 1. In known methods, an aluminum metallization layer 20 is normally knocked down on the component in order to connect the drain zones and to form the bit lines of the memory array. In the method according to the invention, however, a metal barrier layer 19 is applied or knocked down shortly before the aluminum is deposited. This barrier layer extends completely over the active zones and channel zones of the component. In the preferred example, the metal barrier layer 19 is patterned simultaneously with the aluminum metal layer 20, so that the edges of the layers 19 and 20 are substantially together menfallen. Alternatively, the barrier layer 19 and the metal layer 20 can be defined using separate masking steps. Finally, the entire component is passivated using an insulating layer 21 , which consists of an oxide nitride in the example described.

The metal barrier layer 19 consists of a substance which has an affinity for hydrogen atoms. In this way, the metal barrier layer 19 acts as a "block" or "getter" for hydrogen and effectively prevents hydrogen from diffusing into the active or channel zones of the device. A common source of hydrogen atoms in a semiconductor process is the passivation layer 21 , which typically contains silicon oxide or oxynitride. Without a metal barrier layer with a certain affinity for hydrogen atoms, the latter would easily diffuse under the metallization layer (generally at the metallization / field oxide boundary layer) and then migrate into the channel region 12 . There they create interface states that are partly responsible for the excessive charge loss during the cyclic operation.

In the example described, layer 19 contains titanium. Other titanium rich compounds such as titanium nitride or titanium tungsten can also be used. Basically, any metal with an affinity for hydrogen can be used, or a metal that presents a sufficient number of loose bonds to trap hydrogen. The thickness of the titanium in the example described is approximately 150 nm for a 1 μm thick aluminum layer. It is believed that any layer thickness greater than 10 nm is sufficient to adequately reduce the degradation effects associated with hot electron cycling.

As indicated, the metal barrier layer 19 is formed shortly before the metallization layer 20 is deposited. This metal barrier layer is applied using one of several known precipitation methods. For example, in the example described, titanium is sputtered onto the disk. Aluminum is then deposited on the disc and both the titanium and aluminum are patterned simultaneously to form the interconnect lines (e.g., the bit lines).

It should be noted that in some known methods, titanium-tungsten is deposited near the drain contact, for the purpose of preventing aluminum migration into the silicon and for making a contact with low electrical resistance to the drain zone. In these processes, however, the tungsten layer usually does not extend beyond the edges of the contact opening. Conversely, the titanium barrier layer according to the invention extends over the entire active part of the field effect component and is generally formed simultaneously with the aluminum metallization layer 20 . This serves the purpose of a barrier layer to prevent the introduction of hydrogen atoms in the device.

FIG. 2 shows a partial top view of the flash memory cell according to FIG. 1. The floating gate is shown as a dashed zone 16 , while the layer 17 , which forms the control gate, is shown in the memory field as a word line. The bit line, which is formed by the aluminum metal layer 20 , extends at a right angle to the polysilicon word line 17 .

The titanium barrier layer is again shown as layer 19 (for purposes of illustration, the edges of layers 19 and 20 are shown slightly spaced apart. In the preferred example, however, both layers are etched simultaneously so that their edges essentially coincide. ) When a subsequent layer of protective metal is formed over the channel and active zones of the flash memory component, the titanium layer 19 reduces the amount of hydrogen atoms diffusing into the oxide zones 22-24 . Therefore, the barrier layer 19 acts in the sense of maintaining the integrity of the oxide 24 in the tunnel zone between the floating gate 16 and the drain zone 10 . Using the method according to the invention, flash EPROM cells according to FIGS. 1 and 2 can be repeatedly recharged cyclically without experiencing the degradation effects which are normally associated with hot-electron components.

While the edges of the aluminum metallization layer 20 approximately coincide with those of the titanium barrier layer 19 as shown in FIG. 2, it is easy to see that the invention can be used with the same function even if one layer extends beyond the other. Other patterns or relationships between the aluminum and titanium layers are also possible. For the purpose of blocking or gettering hydrogen, the titanium barrier layer 19 only needs to adequately cover the active and channel zones of the component provided with a floating gate electrode. Different metal barrier patterns can therefore be used within the scope of the inventive concept.

In the following, 3A and 3B to FIGS. Taken, in which the boundary shift and the threshold voltage (V _T) postponements for 4000 cycle units, followed by a heat treatment at 250 ° C for 48 hours are shown.

(The 250 ° heat treatment for 48 hours is a common treatment for accelerating the half-life of a semiconductor device.) The limit shift is a measure of the charge loss that can occur in a flash memory and represents a change in the IV characteristics stics of the component. Generally, a larger limit shift corresponds to a greater charge loss in the component. The data for Figure 3A was taken from a group of devices fabricated using the method described above without the titanium barrier layer. The components shown in FIG. 3B were prepared in an identical manner The ones shown in Fig. 3A, with the exception that a titanium barrier layer prior to deposition of the aluminum has been applied prior invention lie in an additional step according to the teaching. A comparison of FIGS. 3A and 3B shows that the limit shift for those components which were produced with a titanium barrier layer is substantially smaller than that for components without such a layer. The voltage threshold ( V _T ) shift, another measure of charge loss, is roughly comparable in both cases. The increased margin shift in the known devices implies that there is an increased amount of apparent charge loss in these devices made without the titanium barrier layer.

FIGS. 4A and 4B show erase time push-outs for the two groups of components mentioned above (ie for those without a titanium barrier layer and those with a titanium barrier layer). The data according to FIG. 4A represent the values for components according to the conventional manufacturing process and show an erasure time push-out which is approximately three times greater in comparison to those components which are produced with a titanium barrier ( FIG. 4B) after 5000 cycles of approximately 0.4 seconds.

Various modifications are within the scope of the inventive concept possible. So metal barrier layers are different patterns and shapes as well as size relations possible. Other elements Compounds or alloys can replace titanium to step.

Claims (11)

1. A method for reducing hot electron-induced degradation effects in a field effect semiconductor component, characterized in that a metal barrier layer ( 19 ) is deposited over active zones ( 10 , 11 , 12 ) of the component, the metal tall- Barrier layer ( 19 ) has an affinity for hydrogen such that it reduces the number of hydrogen atoms in the vicinity of the active zones of the device, and that the metal barrier layer ( 19 ) is patterned. 2. The method according to claim 1, characterized in that a gate component ( 16 ) is formed over the channel zone ( 12 ) and insulated from the substrate ( 13 ), that drain and source zones ( 10 , 11 ) are formed in the substrate whereby a channel region ( 12 ) is defined, that afterwards the metal barrier layer ( 19 ) is deposited at least over the channel region ( 12 ) and that afterwards a metallization layer ( 20 ) for establishing an electrical contact with the source or drain Zones ( 10 or 11 ) is knocked down. 3. A method for producing an electrically programmable and electrically erasable memory component with reduced hot-electron-induced degradation effects during repeated reloading of the memory component, characterized in that

• a) that a metal barrier layer ( 19 ) is deposited on a semiconductor substrate such that it spans at least the active zones ( 10 , 11 , 12 ) of the component and is in electrical contact with certain substrate zones ( 10 ), the metal barrier layer has an affinity for hydrogen such that the presence of hydrogen atoms near the active zones of the device is reduced;
• b) that a metallization layer ( 20 ) is applied over at least part of the metallic barrier layer ( 19 ) in order to produce an electrical connection to the component; and
• c) that the first and second metal layers ( 19 , 20 ) are patterned to produce electrical connections.

4. A method for forming a field of electrically programmable or electrically erasable memory components in the form of flash memory cells, characterized in that

• a) a plurality of gate electrodes ( 16 , 17 ) are formed via channel zones ( 12 ) isolated from the substrate ( 13 );
• b) source and drain zones ( 11 , 10 ) are formed in the substrate and thus a plurality of channel zones ( 12 );
• c) a metal barrier layer ( 19 ) is deposited over at least the source or drain zones,
• d) that thereafter a metallization layer ( 20 ) for forming bit and word lines is deposited in the memory field, the metallization layer being in electrical contact with the source or drain zones; and
• e) that the memory field is passivated.

5. The method according to any one of claims 1 to 4, characterized in that the metal barrier layer ( 19 ) contains a titanium compound. 6. The method according to any one of claims 1 to 5, characterized in that the metal barrier layer ( 19 ) is selected from the group consisting of titanium, titanium nitride and titanium-tungsten. 7. The method according to any one of claims 1 to 6, characterized in that the metal barrier layer ( 19 ) is deposited in a thickness between 10 and 300 nm. 8. The method according to claim 7, characterized in that the metal barrier layer ( 19 ) has a thickness of about 150 nm. 9. The method according to any one of claims 1 to 8, characterized in that the metal barrier layer ( 19 ) is patterned such that its edges coincide essentially with those of the metallization layer ( 20 ). 10. The method according to any one of claims 1 to 9, characterized in that the metal barrier layer ( 19 ) covers both the drain and source zones ( 10 , 11 ) and the channel zone ( 12 ) of the component. 11. The method according to any one of claims 1 to 10, characterized characterized in that a flash EEPROM as the memory component is used.