DE3878376D1 - Programmierbares muldex. - Google Patents

Programmierbares muldex.

Info

Publication number
DE3878376D1
DE3878376D1 DE8888116068T DE3878376T DE3878376D1 DE 3878376 D1 DE3878376 D1 DE 3878376D1 DE 8888116068 T DE8888116068 T DE 8888116068T DE 3878376 T DE3878376 T DE 3878376T DE 3878376 D1 DE3878376 D1 DE 3878376D1
Authority
DE
Germany
Prior art keywords
muldex
programmable
programmable muldex
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888116068T
Other languages
English (en)
Other versions
DE3878376T2 (de
Inventor
Toshiaki Watanabe
Kazuo Murano
Tetsuo Soejima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP24427987A external-priority patent/JPS6489746A/ja
Priority claimed from JP62244283A external-priority patent/JPS6489716A/ja
Priority claimed from JP62244278A external-priority patent/JPS6488759A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3878376D1 publication Critical patent/DE3878376D1/de
Publication of DE3878376T2 publication Critical patent/DE3878376T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1623—Plesiochronous digital hierarchy [PDH]
    • H04J3/1641—Hierarchical systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DE8888116068T 1987-09-30 1988-09-29 Programmierbares muldex. Expired - Fee Related DE3878376T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP24427987A JPS6489746A (en) 1987-09-30 1987-09-30 Serial/parallel converter
JP62244283A JPS6489716A (en) 1987-09-30 1987-09-30 Clock phase synchronization circuit
JP62244278A JPS6488759A (en) 1987-09-30 1987-09-30 Data input/output processing system

Publications (2)

Publication Number Publication Date
DE3878376D1 true DE3878376D1 (de) 1993-03-25
DE3878376T2 DE3878376T2 (de) 1993-07-29

Family

ID=27333222

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888116068T Expired - Fee Related DE3878376T2 (de) 1987-09-30 1988-09-29 Programmierbares muldex.

Country Status (4)

Country Link
US (1) US4975913A (de)
EP (1) EP0310066B1 (de)
CA (1) CA1299783C (de)
DE (1) DE3878376T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03126131A (ja) * 1989-10-11 1991-05-29 Nec Corp 中央処理装置の実行速度制御方式
JP2599819B2 (ja) * 1990-11-02 1997-04-16 富士通株式会社 データリンク終端方式
EP0562251A2 (de) * 1992-03-24 1993-09-29 Universities Research Association, Inc. Durch ein dynamisches wiederkonfigurierbares serielles Netzwerk gesteuertes Paralleldatenübertragungsnetzwerk
US5331315A (en) * 1992-06-12 1994-07-19 Universities Research Association, Inc. Switch for serial or parallel communication networks
GB2280338B (en) * 1993-07-16 1997-09-24 Motion Media Techn Ltd Multiple bit stream multiplexor/demultiplexor for communication channels
EP0687986A3 (de) * 1994-06-17 1996-02-14 Ibm Verfahren und Anordnung zur digitalen Datenübertragung in massiv-parallelen Systemen
KR0138327B1 (ko) * 1994-12-19 1998-06-15 김광호 데이타 전송장치
GB2330736B (en) * 1997-10-24 2002-04-10 Mitel Corp Timing recovery with minimum jitter movement

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4330863A (en) * 1978-07-07 1982-05-18 Wright Simon C M Demodulator arrangement
US4280099A (en) * 1979-11-09 1981-07-21 Sperry Corporation Digital timing recovery system
EP0067384A3 (de) * 1981-06-17 1984-01-04 Digital Equipment Corporation Schaltkreis zur Serialisierung und Deserialisierung von digitalen Daten
US4445215A (en) * 1982-03-05 1984-04-24 Ampex Corporation Programmable frequency ratio synchronous parallel-to-serial data converter
US4546486A (en) * 1983-08-29 1985-10-08 General Electric Company Clock recovery arrangement
US4627080A (en) * 1984-11-23 1986-12-02 At&T Bell Laboratories Adaptive timing circuit
ATE87160T1 (de) * 1985-12-18 1993-04-15 Advanced Micro Devices Inc System fuer das uebertragen und empfangen von asynchronen paralleldaten von nichthomogener variabler breite ueber ein synchrones serienuebertragungsmittel mit hoher informationsgeschwindigkeit.
JPS62276935A (ja) * 1986-01-07 1987-12-01 Fujitsu Ltd 多重化装置

Also Published As

Publication number Publication date
CA1299783C (en) 1992-04-28
EP0310066B1 (de) 1993-02-10
DE3878376T2 (de) 1993-07-29
US4975913A (en) 1990-12-04
EP0310066A2 (de) 1989-04-05
EP0310066A3 (en) 1989-06-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee