DE3855157T2 - Amplifier circuitry - Google Patents

Description

This invention relates to an amplifier circuit arrangement comprising a first and second stage in cascade, the first stage having a long tail pair of first and second transistors of the same conductivity type and first and second resistors connecting the output electrodes of said first and second transistors to a first voltage reference point, respectively, and the second stage having a current amplifier circuit and a third resistor, the end of the output electrode of said first resistor being connected via said third resistor and in that order via the current input line of said current amplifier circuit to a second voltage reference point, and the end of the output electrode of said second resistor being connected via the current output line of said current amplifier circuit to a second voltage reference point.

Long transistor tail pairs are often used in amplifier circuit arrangements, particularly when the arrangements are in the form of integrated circuits. Individual integrated circuit fabrication techniques tend to prefer to fabricate transistors of a particular conductivity type rather than transistors of the opposite conductivity type, e.g. because those of the particular conductivity type give the form of so-called "vertical" transistor structures, while those of the opposite conductivity type give the form of so-called "lateral" transistors. "Vertical" transistor structures tend to give higher power and higher cut-off frequencies than "lateral" transistor structures, with the result that in many applications it is common to avoid the use of "lateral" transistors altogether if possible. However, other considerations sometimes come into play which work against this. One of these is the requirement in some applications that the noise superimposed on the voltage supply of the arrangement should be absent or insignificant in the output signal of the arrangement. An amplifier arrangement of the general type described in this first section is known from the patent US-A-4 710 728. In this known amplifier, the (differential) output of the first stage is formed by the ends of the output electrode of the first and second resistors. Of course, the signal voltages appearing at these points, as they are respectively established between the first and second resistors, are relative to the first voltage reference points. Thus, when said signal voltage is applied to the test electrode of a third transistor of the common electrode connected to the first voltage reference point, noise appearing at the first voltage reference point will have no effect on the signal appearing between said test electrode and the voltage electrode. In practice, however, this would mean that unless the provision of, for example, more than two supply voltages could be tolerated, the third transistor would have to be of the inverse conductivity type to said equal conductivity type, which, as mentioned above, is often unsatisfactory. An object of the invention is to make it possible to mitigate this problem.

According to the invention, the amplifier circuit arrangement defined in the first paragraph has the features that a fourth resistor is included in series between the end of the output electrode of the second resistor and the current output line of the current amplifier circuit, that the end of the current output line of said fourth resistor forms an output of the second stage and that the resistance values of the first, second, third and fourth resistors and the power of said current amplifier are selected so that in operation the voltage at the output of the second stage is fundamentally independent of voltage variations of the first voltage reference point with respect to the voltage of the second voltage reference point.

An article by Carlos A. Laber et al, entitled Design Considerations for a High-Performance 3-µm CMOS Analogue Standard-Cell Library, published in the IEEE Journal of Solid State Circuits, Volume SC-22, April 2, 1987, pages 181 to 189, reveals in Figure 6a) on page 186 a circuit configuration similar to that described in the first and previous paragraphs.

It is now recognized that if the second stage is arranged in a configuration as described above with a suitable choice of the resistance values and the power of the current amplifier, the output of the first stage can be so output of the second stage such that noise appearing at the first voltage reference point with respect to the second voltage reference point has little or no effect on the signal appearing at the output of the second stage with respect to the second voltage reference point. If the voltage sign between the first and second voltage reference points is correctly chosen, the output signal of the second stage (which may itself comprise transistors of said same conductivity type) may in turn be fed, for example, to the test electrode of another transistor of said same conductivity type, the common electrode of which is connected to the second voltage reference point (to which, for simplicity, the "tail" of the long tail pair may be connected).

The terms "test electrode", "output electrode" and "common electrode" are to be understood here as "base electrode", "collector electrode" and "emitter electrode" respectively when the transistor in question is a bipolar transistor, and as "gate electrode", "drain electrode" and "source electrode" respectively when the transistor in question is a field effect transistor. The power G of the current amplification stage can of course be less than, equal to or greater than unity.

The second stage may comprise third and fourth transistors of said same conductivity type, the output electrodes of said third and fourth transistors being connected to the first voltage reference point and the test electrode/common electrode leads of said third and fourth transistors being inserted between the end of the output electrode of said first resistor and said third and between the end of said output electrode of said second resistor and said third resistor, respectively. On the other hand, if the values of the third and fourth resistors are high with respect to the values of the first and second resistors, the third and fourth resistors may be connected directly to the first and second resistors, respectively.

Descriptions of embodiments of the invention will now be given by way of example with reference to the accompanying circuit diagram, the only figure of which is a circuit diagram of a specific embodiment.

In the plan, an amplifier circuit arrangement includes a first and second stage 1 and 2 in cascade. The first stage 1 contains a long tail pair of NPN transistors 3 and 4, whose collector electrodes are connected to the first voltage reference point 5 via the first and second resistors 6 and 7 respectively. The connected emitters of the transistors 3 and 4 are connected to a second voltage reference point 8 via a current source 9. The second stage 2 contains a current amplifier circuit 10 in the form of a so-called current mirror circuit. The circuit 10 contains a pair of NPN transistors 11 and 12, whose emitters are connected and connected to point 8. The bases of these transistors are also connected and connected to the collector of transistor 11. The power supply line of circuit 10 runs from the collector/base of transistor 11 to point 8 and the power output line in turn runs from the collector of transistor 12 to point 8. The collector end of resistor 6 is connected to the collector/base of transistor 11 via the base-emitter path of an NPN transistor 13 and a third resistor 14, in that order, and the collector end of resistor 7 is connected to the collector of transistor 12 via the base-emitter path of a transistor 15 and a fourth resistor 16, in that order. The collectors of transistors 13 and 15 are connected to point 8. The common point of resistor 16 and the collector of resistor 12 forms the output 17 of stage 2 and may, if desired, be connected to the base of a further NPN transistor 18 as shown in dashed lines. The resistances R6, R7, R14 and R15 are connected to point 8. and R₁₆ of the respective resistors 6, 7, 14 and 16 are selected together with the current G of the amplifier 10 in conjunction with the currents B₁₃ and B₁₅ of the respective transistors 13 and 15 so that the equation

R₇G(1+B₁₃)/(1+B₁₅). + R₁₆G(1+B₁₃) = R₆ + R₁₄(1+B₁₃)

is fundamentally respected. The reasons for this will become apparent below.

In operation, a positive voltage supply is applied to point 5' with respect to point 8 and an input signal is applied between the bases of transistors 3 and 4 (points 19 and 20 respectively). The resulting differential signal voltages appearing at the collectors of transistors 3 and 4 are applied via the emitter of the follower transistor 13 and the resistor 14 to the power input line of amplifier 10 and via the emitter of the follower transistor 15 and the resistor 16 to the common point of the power output line of amplifier 10 and the output terminal 17. The resulting current signal flowing into the input line of amplifier 10 is, as is known, equal to G times this current signal flowing into the output line of amplifier 10. The overall result is therefore that the output signal of stage 1 is successfully connected to the output 17 of stage 2.

If the voltage at point 5 should differ relative to that at point 8, the base current of transistor 13 will have a difference i. This will result in a change of i(1+B₁₃) in the emitter current of transistor 13 and hence in the current through resistor 14 and the input current line of amplifier 10. Thus there will be a change of Gi(1+B₁₃) in the output current of amplifier 10 and hence in the emitter current of transistor 15 and the current through resistor 16. The resulting change in the base current of transistor 15 is therefore Gi(1+B₁₃)/(1+B₁₅). The voltage change at the output terminal 17 with respect to point 5 is therefore R₇Gi(1+B₁₃)/(1+B₁₅) + R₁₆Gi(1+B₁₃). However, the voltage change v at point 5 with respect to that at point 8 is obtained as v = R₆i + R₁₄i(1+B₁₃). As already mentioned, R₆, R₇, R₁₄, R₁₆ and G have been chosen with respect to B₁₃ and B₁₅, and thus the equation

R₇G(1+B₁₃)/(1+B₁₅) + R₁₆G(1+B₁₃) = R₆ + R₁₄(1+B₁₃)

fundamentally respected; in practice an error of, say, 5% may occur, e.g. due to inevitable tolerances in the circuit elements manufactured using integrated circuit techniques. Thus, the voltage change itself at the output pole 17 with respect to point 5 is fundamentally equal to v. In other words, the voltage change at the output pole 17 with respect to point 8 is fundamentally zero, as required.

The emitter follower transistors 13 and 15, which actually constitute voltage signal sources of the internal resistors R₆/(1+B₁₃) and R₇/(1+B₁₅) connected between the ends of the resistors 14 and 16 and point 5, respectively, are basically provided to reduce the charge imposed on the output of stage 1 by the input of stage 2. If the values of the resistors 14 and 16 are high with respect to the values of the respective resistors 6 and 7, these Emitter followers are omitted, resistor 14 is then connected directly to the collector end of resistor 6, and resistor 16 directly to the collector end of resistor 7, so that resistors 6 and 7 now effectively form themselves the signal voltage sources of the internal resistors R₆ and R₇ connected respectively between the ends of resistors 14 and 16 and point 5 when driven by the long tail pair of transistors. When this is done the result is equal to the expression B₁₃ = B₁₅ = 0 given above, thus causing a reduction of

G(R₇+R₁₆) = R₆ + R₁₄.

If desired, respective capacitors, possibly in series with the respective resistors, may be provided across each of the resistors 14 and 16 to improve the frequency sensitivity of the circuit. In providing them, the ratio between their impedances should be chosen to be equal to the ratio between the corresponding resistors 14 and 16.

The NPN transistors in the circuits described can, of course, be replaced by PNP transistors if the sign of the supply voltage applied between points 5 and 8 is reversed. Another possibility is to replace them by N-channel field effect transistors (or P-channel field effect transistors if the sign of the supply voltage is reversed) whose gates, drains and sources correspond to the respective bases, collectors and emitters of the bipolar transistors described. The simple current mirror arrangement shown for amplifier 10 can, of course, be replaced by another type of current amplifier circuit, for example by one of the numerous other current mirror circuits well known to persons skilled in the art.

Upon review of this disclosure, persons skilled in the art will recognize other changes. These changes may involve other features whose designs, manufacture, and use in circuit arrangements are already known and which may be used instead of or in addition to the features already described herein.

Claims (5)

1. An amplifier circuit arrangement having a first and second stage in cascade, the first stage having a long tail pair of first and second transistors of the same conductivity type and first and second resistors connecting the output electrodes of said first and second transistors to a first voltage reference point, respectively, and the second stage having a current amplifier circuit and a third resistor, the end of the output electrode of said first resistor being connected to a second voltage reference point via said third resistor and in that order via the current input line of said current amplifier circuit, and the end of the output electrode of said second resistor being connected to a second voltage reference point via the current output line of said current amplifier circuit, with the feature that a fourth resistor is included in series between the end of the output electrode of the second resistor and the current output line of the current amplifier circuit, that the end of the current output line of said fourth resistor forms an output of the second stage, and, that the resistance values of the first, second, third and fourth resistors and the power of the said current amplifier are selected such that, during operation, the voltage at the output of the second stage is fundamentally independent of voltage variations of the first voltage reference point with respect to the voltage of the second voltage reference point. 2. An arrangement according to claim 1, wherein the second stage comprises transistors all of the same conductivity type. 3. An arrangement according to claim 1 or claim 2, wherein the second stage may comprise third and fourth transistors of said same conductivity type, the output electrodes of said third and fourth transistors being connected to the first voltage reference point and the test electrode/common electrode leads of said third and fourth transistors being connected between the end of the output electrode of said first resistor and the said third and respectively inserted between the end of said output electrode of said second resistor and said third resistor. 4. An arrangement according to claim 1 or claim 2, wherein the resistance values of said third and fourth resistors are high with respect to the resistance values of said respective first and second resistors and the third and fourth resistors are connected directly to the respective first and second resistors. 5. An arrangement according to any preceding claim, wherein the tail of the long tail pair is connected to the second voltage reference point.