DE3842694A1 - DEMULTIPLEXER WITH CIRCUIT TO REDUCE THE WAITING JITTER - Google Patents

Abstract

There are time-division multiplex communication systems in which digital signals which are asynchronous with the pulse frame and consist of successive blocks whose beginnings are marked with sync words are inserted into the pulse frame. The resulting jitter of the sync words ("waiting-time jitter") is reduced by a circuit which derives from the clock of the received sync words a sync signal (SY) that exhibits less jitter than the clock of the received sync words. According to the invention, the circuit contains a measuring device which measures the time intervals (N) between the sync words, a filter (F) which takes the average (N') of the time intervals (N), and a signal generator (S) which forms the sync signal (SY) from said average (N') in such a manner that the pulse period of the sync signal (SY) is equal to said average (N').

Description

The invention relates to a demultiplexer according to the Preamble of claim 1.

Such a demultiplexer is known from the DE-A1-34 39 633. In the described there Demultiplexer is the synchronous signal from Word clock of the received sequence of synchronous words derived that using a demultiplexer transmitted additional information the word clock in such a way is corrected that the distances between his successive clock pulses equal to the intervals of the synchronous words of the multiplexer in the transmission side the pulse frame to be inserted, asynchronous to the pulse frame Are digital signal. The through to the pulse frame caused asynchronous insertion of this signal Clock fluctuation of the synchronous words, the so-called "Waiting time jitter" thus becomes clear in the demultiplexer decreased.

The disadvantage of this solution is that a transmission side Circuit for generating the additional information necessary is and that through their transmission Transmission capacity is lost.

It is therefore the object of the invention, one Demultiplexer specify the reduction in Waiting time jitters without, in the associated transmitter-side multiplexer any measures for this must be taken.

The object is achieved as in claim 1 specified. Further training results from the Subclaims.

The invention is based on the figures, for example explained. It shows

Fig. 1 is a block diagram of the new circuit for reducing the waiting time jitter;

Fig. 2 shows a first embodiment of the filter F shown in Fig. 1,

Fig. 3 shows a second embodiment of the filter F shown in Fig. 1.

Referring to FIG. 1, when (not shown here) in the synchronous word detector, a synchronous word has been detected, a current generated in the synchronous word detector for the synchronizing word pulse measuring means M supplied doubly I.

The measuring device M contains a counter 1 and a register 2 .

After receipt of a pulse I , clocked by a word clock WT provided by the demultiplexer (not shown ), the counter 1 counts the number of clock pulses from zero to the next pulse I. It then has reached a counter reading N _n , which is a measure of the time interval between these two pulses, that is, between the two consecutive received synchronous words. Different counter readings N _i ; i = 0, 1, 2,. . ., m,. . ., n,. . .

This counter reading N _n is transferred to register 2 , which is controlled by the last pulse I.

From register 2 , the counter reading N _n reaches a filter F, which is also controlled by the pulse.

The filter F forms from the last received counter reading together with a fixed number of previously received counter readings a rounded to an integer N ' .

This is fed to a signal generator S , which consists of a down counter 3 and a comparator 4 . Upon receipt of the mean value N ', the down counter 3 , clocked by the word clock WT or by an integer multiple of the word clock WT , counts down from the mean value N' to zero. Each numerical value is fed to the comparator 4 , which compares it with the numerical value zero. When zero is reached, the comparator generates a synchronizing signal SY from the numerical value, more precisely: the edge of a synchronizing signal SY , the clock period of the synchronizing signal SY being equal to the mean value N ' . The synchronizing signal SY serves as a phase locked loop (PLL) as an input signal. It is returned to the down counter 3 so that it can record the next average N ' from the filter F.

FIG. 2 shows a first exemplary embodiment of the filter F from FIG. 1.

A counter reading N _n becomes both an adder 21 , where it is added to a sum of the register 2 shown in FIG. 1 from m summands of the last counter readings up to N _{n -1}

as well as a shift register 22 , in which the last m counter readings N _nm to N _{n -1 are} contained.

Whenever the shift register 22 is triggered by a pulse I , the counter readings N _i are shifted by one storage location, the new counter reading N _{n is set} in the free storage location of the counter reading N _{n -1} , and the "oldest" counter reading N _nm becomes given to a subtractor 23 .

This has two inputs, one of which is connected to the output of the shift register 22 , the other to the output of the adder 21 . It forms the difference from the sum

from the output of the adder 21 and the count N _{nm of} the shift register 22 :

The difference formed by the subtractor 23 is fed to a register 24 , which is clocked again by the pulses I. From there it arrives on the one hand at a further adder 25 , on the other hand back to the adder 21 , in this way the new sum

is formed.

The sum of the difference and a rounding error R is formed in the adder 25 . The sum is fed to a computing circuit 26 with two outputs, which forms the arithmetic mean of the counter readings N _i and rounds the value obtained to an integer N ' , forwards this to the signal generator S (see FIG. 1) and the rounding error R one Register 25 feeds, which, clocked by the pulses I , supplies the rounding error from the previous rounding to the adder 31 at the same time as a new sum arrives.

The rounding errors R are used to maintain the clock repetition frequency on average.

Another embodiment of the filter F is shown in FIG. 3.

On the input side, it contains an adder 31 , which forms the sum of the last counter reading N _n from register 2 ( FIG. 1) and an error signal FS from a register 35 .

This is fed to an input of a comparator 32 with two inputs and a subtractor 34 . The comparator 32 receives, via its other input, the counter reading from the output of a counter 33 , which it compares with the value from the adder 31 . If this is less than the counter reading of the counter 33 , the comparator 32 lowers its counter reading by 1; conversely, if the value from the adder 31 is greater than the counter reading of the counter 33 , it increases its counter reading. If both values are the same, he leaves it. The counter 33 is set to an assumed average counter reading via a line L before the circuit is started up, so that the filter F can work from the beginning.

The counter 33 is clocked by the pulses I. Its output is connected to the input of the signal generator S shown in FIG. 1 and the subtractor 34 .

The subtractor 34 forms the difference between the counter reading of the counter 33 and the sum obtained from the adder 31 . The difference formed by the subtractor 34 represents the error signal FS , which is fed to the register 35 clocked by the pulses I , which it supplies to the adder 31 when the next counter reading N _{n +1} arrives. The adder 31 then again forms the sum of the counter reading N _{n +1} and the error signal FS.

In this way, an average counter reading N ' can be set in the counter 33 . The counter therefore passes on the output side much smaller fluctuations in the counter readings to the signal generator S than are present on the adder 31 on the input side.

Claims (3)

1. Demultiplexer for a digital time-division multiplex message transmission system, in which a digital signal asynchronous to the pulse frame, which consists of successive blocks, the block beginnings of which are each marked by a synchronous word, is inserted into the pulse frame, with a circuit which consists of the clock of the received sequence derives the synchronous words from a synchronous signal (SY) which has a lower clock fluctuation than the clock of the received sequence of synchronous words, characterized in that it contains: a measuring device (M) which measures the time intervals (N) between the received synchronous words Filter (F) , which forms a mean (N ') from the time intervals (N) of the synchronous words, and a signal generator (S) which forms a synchronous signal (SY) from the mean (N' ) in such a way that its clock period is the same is the mean (N ′) . 2. Demultiplexer according to claim 1, characterized in that the filter (F) forms the arithmetic mean (N ') over the distances of the different time intervals (N _i ) successive synchronous words measured in the course of a predetermined period of time, and it to a whole Number N ' rounds, taking into account the rounding error (R) that arises during the averaging process by means of error feedback for the subsequent averaging. 3. Demultiplexer according to claim 1, characterized in that the filter (F) contains a counter ( 33 ), in which an assumed average distance of synchronous words is stored before the circuit is put into operation, that the counter ( 33 ) only once during a distance between two synchronous words can increase or decrease the counter reading (N ') it contains by a fixed amount or that the change in the result of a number comparison between the counter reading (N') stored in the counter ( 33 ) on the one hand and the sum of one , at the input of the filter (F) following counter reading (N _{n +1)} and an error signal (FS) on the other hand is determined.