DE3787638D1 - Steuereinrichtung zur speicherung von adressen in einem adressenuebersetzungspufferspeicher. - Google Patents

Steuereinrichtung zur speicherung von adressen in einem adressenuebersetzungspufferspeicher.

Info

Publication number
DE3787638D1
DE3787638D1 DE87119015T DE3787638T DE3787638D1 DE 3787638 D1 DE3787638 D1 DE 3787638D1 DE 87119015 T DE87119015 T DE 87119015T DE 3787638 T DE3787638 T DE 3787638T DE 3787638 D1 DE3787638 D1 DE 3787638D1
Authority
DE
Germany
Prior art keywords
control device
address translation
buffer storage
translation buffer
storing addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE87119015T
Other languages
English (en)
Other versions
DE3787638T2 (de
Inventor
Kouji C O Nec Corpor Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE3787638D1 publication Critical patent/DE3787638D1/de
Application granted granted Critical
Publication of DE3787638T2 publication Critical patent/DE3787638T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE87119015T 1986-12-23 1987-12-22 Steuereinrichtung zur Speicherung von Adressen in einem Adressenübersetzungspufferspeicher. Expired - Fee Related DE3787638T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30736186 1986-12-23

Publications (2)

Publication Number Publication Date
DE3787638D1 true DE3787638D1 (de) 1993-11-04
DE3787638T2 DE3787638T2 (de) 1994-04-28

Family

ID=17968162

Family Applications (1)

Application Number Title Priority Date Filing Date
DE87119015T Expired - Fee Related DE3787638T2 (de) 1986-12-23 1987-12-22 Steuereinrichtung zur Speicherung von Adressen in einem Adressenübersetzungspufferspeicher.

Country Status (3)

Country Link
EP (1) EP0275530B1 (de)
AU (1) AU608796B2 (de)
DE (1) DE3787638T2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5125083A (en) * 1989-02-03 1992-06-23 Digital Equipment Corporation Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4520441A (en) * 1980-12-15 1985-05-28 Hitachi, Ltd. Data processing system

Also Published As

Publication number Publication date
EP0275530B1 (de) 1993-09-29
EP0275530A2 (de) 1988-07-27
EP0275530A3 (en) 1990-06-20
AU608796B2 (en) 1991-04-18
DE3787638T2 (de) 1994-04-28
AU8291687A (en) 1988-06-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee